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參數資料
| 型號： | IDT72825LB15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
| 中文描述： | 1K X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數： | 20/26頁 |
| 文件大小： | 334K |
| 代理商： | IDT72825LB15PF |
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
20
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. n =
PAE
offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. t
SKEW2
is the mnimumtime between a rising WCLK edge and a rising RCLK edge for
PAE
to go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than t
SKEW2
, then the
PAE
deassertion may be delayed one extra RCLK cycle.
5.
PAE
is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (
FL
,
RXI
,
WXI
) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
NOTES:
1. m=
PAF
offset.
2. D = maximumFIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72805, 512 for the IDT72815, 1,024 for the IDT72825, 2,048 for the IDT72835 and 4,096 for the IDT72845.
In FWFT Mode:
D = 257 for the IDT72805, 513 for the IDT72815, 1,025 for the IDT72825, 2,049 for the IDT72835 and 4,097 for the IDT72845.
3. t
SKEW2
is the mnimumtime between a rising RCLK edge and a rising WCLK edge for
PAF
to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than t
SKEW2
, then the
PAF
deassertion time may be delayed an extra WCLK cycle.
4.
PAF
is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (
FL
,
RXI
,
WXI
) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAE
RCLK
REN
3139 drw 22
t
ENS
t
ENH
t
ENS
n words in FIFO
(2)
,
n + 1words in FIFO
(3)
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
t
SKEW2
t
PAES
n Words in FIFO
(2)
,
n + 1 words in FIFO
(3)
(4)
t
PAES
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAF
RCLK
REN
3139 drw 23
t
ENS
t
ENH
t
ENS
D-(m+1) Words in
FIFO
D - m Words in FIFO
D -(m+1) Words
in FIFO
t
PAFS
t
PAFS
t
SKEW2
(3)
相關PDF資料 |
PDF描述 |
|---|---|
| IDT72825LB15PFI | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
| IDT72825LB20BGI | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
| IDT72845LB | Precision Micropower Shunt Voltage Reference 5-SC70 -40 to 85 |
| IDT72845LB10PF | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
| IDT72845LB10PFI | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT72825LB15PF8 | 功能描述:IC FIFO SYNC DL 1024X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72825LB15PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC DL 1024X18 128TQFP |
| IDT72825LB15PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC DL 1024X18 128TQFP |
| IDT72825LB15PFI | 功能描述:IC FIFO SYNC DL 1024X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72825LB15PFI8 | 功能描述:IC FIFO SYNC DL 1024X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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