參數(shù)資料
型號(hào): IDT72821L25PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: DUAL CMOS SyncFIFO
中文描述: 1K X 9 BI-DIRECTIONAL FIFO, 15 ns, PQFP64
封裝: TQFP-64
文件頁數(shù): 8/21頁
文件大?。?/td> 228K
代理商: IDT72821L25PF
5.15
8
COMMERCIAL TEMPERATURE
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
OUTPUTS:
Full Flag (
FFA
further write operations, when Array A (B) is full. If no reads
are performed after reset,
FFA
(
FFB
) will go LOW after 256
writes to the 72801's FIFO A (B), 512 writes to the 72811's
FIFO A (B), 1024 writes to the 72821's FIFO A (B), 2048 writes
to the 72831's FIFO A (B), or 4096 writes to the 72841's FIFO
A (B).
FFA
(
FFB
) is synchronized with respect to the LOW-to-
HIGH transition of the write clock WCLKA (WCLKB).
,
FFB
)
FFA
(
FFB
) will go LOW, inhibiting
Empty Flag (
EFA
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating that Array A (B) is empty.
EFA
(
EFB
) is synchronized with respect to the LOW-to-
HIGH transition of the read clock RCLKA (RCLKB).
,
EFB
)
EFA
(
EFB
) will go LOW,
Programmable Almost–Full Flag (
(
PAFB
) will go LOW when the amount of data in Array A (B)
reaches the Almost-Full condition. If no reads are performed
after reset,
PAFA
(
PAFB
) will go LOW after (256-m) writes to
the 72801's FIFO A (B), (512-m) writes to the 72811's FIFO A
(B), (1024-m) writes to the 72821's FIFO A (B), (2048-m)
PAFA
,
PAFB
)
PAFA
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
72801
0
1 to n
(1)
(n+1) to (256-(m+1))
(n+1) to (512-(m+1))
(256-m)
(2)
to 255
(512-m)
(2)
to 511
256
FFA
FFB
PAFA
PAFB
PAEA
PAEB
EFA
EFB
72811
0
1 to n
(1)
72821
0
1 to n
(1)
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
L
H
H
H
H
(n+1) to (1024-(m+1))
(1024-m)
(2)
to 1023
1024
512
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
72831
0
1 to n
(1)
(n+1) to (2048-(m+1))
(2048-m)
(2)
to 2047
2048
FFA
FFB
PAFA
PAFB
PAEA
PAEB
EFA
EFB
72841
0
1 to n
(1)
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
L
H
H
H
H
(n+1) to (4096-(m+1))
(4096-m)
(2)
to 4095
4096
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
3034 tbl 09
writes to the 72831's FIFO A (B), or (4096-m) writes to the
72841's FIFO A (B).
FFA
(
FFB
) is synchronized with respect to the LOW-to-
HIGH transition of the write clock WCLKA (WCLKB). The
offset “m” is defined in the Full Offset Registers.
If there is no Full offset specified,
PAFA
(
PAFB
) will go LOW
at Full-7 words.
PAFA
(
PAFB
) is synchronized with respect to the LOW-to-
HIGH transition of the write clock WCLKA (WCLKB).
Programmable Almost–Empty Flag (
PAEA
(
PAEB
) will go LOW when the read pointer is "n+1"
locations less than the write pointer. The offset "n" is defined
in the Empty Offset Registers. If no reads are performed after
reset,
PAEA
(
PAEB
) will go HIGH after "n+1" writes to FIFO A
(B).
If there is no Empty offset specified,
PAEA
(
PAEB
) will go
LOW at Empty+7 words.
PAEA
(
PAEB
) is synchronized with respect to the LOW-to-
HIGH transition of the read clock RCLKA (RCLKB).
PAEA
,
PAEB
)
Data Outputs (QA
0
– QA
8,
QB
0
– QB
8
)
— QA
0
- QA
8
are
the nine data outputs for memory array A, QB
0
- QB
8
are the
nine data outputs for memory array B
.
相關(guān)PDF資料
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