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| 型號： | IDT72615L25PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SyncBiFIFOO 256 x 18 x 2 and 512 x 18 x 2 |
| 中文描述： | 512 X 18 BI-DIRECTIONAL FIFO, 15 ns, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 209K |
| 代理商： | IDT72615L25PF |
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
5.18
4
PIN DESCRIPTION
Symbol
D
A0
-D
A17
CS
A
R/
W
A
Name
I/O
I/O
I
I
Description
Data A
Chip Select A
Read/Write A
Data inputs & outputs for the 18-bit Port A bus.
Port A is accessed when
CS
A
is LOW. Port A is inactive if
CS
A
is HIGH.
This pin controls the read or write direction of Port A. If R/
W
A
is LOW, Data A input data is
written into Port A. If R/
W
A
is HIGH, Data A output data is read from Port A. In bypass mode,
when R/
W
A
is LOW, message is written into A
→
B output register. If R/
W
A
is HIGH, message
is read from B
→
A output register.
CLK
A
is typically a free running clock. Data is read or written into Port A on the rising edge of
CLK
A
.
When
EN
A
is LOW, data can be read or written to Port A. When
EN
A
is HIGH, no data
transfers occur.
When R/
W
A
is HIGH , Port A is an output bus and
OE
A
controls the high-impedance state of
D
A0
-D
A17
. If
OE
A
is HIGH, Port A is in a high-impedance state. If
OE
A
is LOW while
CS
A
is
LOW and R/
W
A
is HIGH, Port A is in an active (low-impedance) state.
When
CS
A
is asserted, A
0
, A
1
, A
2
and R/
W
A
are used to select one of six internal resources.
Data inputs & outputs for the 18-bit Port B bus.
This pin controls the read or write direction of Port B. If R/
W
B
is LOW, Data B input data is
written into Port B. If R/
W
B
is HIGH, Data B output data is read from Port B. In bypass mode,
when R/
W
B
is LOW, message is written into B
→
A output register. If R/
W
B
is HIGH, message
is read from A
→
B output register.
Clock B is typically a free running clock. Data is read or written into Port B on the rising edge
of CLK
B
.
When
EN
B
is LOW, data can be read or written to Port B. When
EN
B
is HIGH, no data
transfers occur.
When R/
W
B
is HIGH , Port B is an output bus and
OE
B
controls the high-impedance state of
D
B0
-D
B17
. If OE
B
is HIGH, Port B is in a high-impedance state. If
OE
B
is LOW while R/
W
B
is HIGH, Port B is in an active (low-impedance) state.
When
EF
AB
is LOW, the A
→
B FIFO is empty and further data reads from Port B are inhibited.
When
EF
AB
is HIGH, the FIFO is not empty.
EF
AB
is synchronized to CLK
B
. In the bypass
mode,
EF
AB
HIGH indicates that data D
A0
-D
A17
is available for passing through. After the
data D
B0
-D
B17
has been read,
EF
AB
goes LOW.
When
PAE
AB
is LOW, the A
→
B FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into
PAE
AB
Register. When
PAE
AB
is HIGH, the
A
→
B FIFO contains more than offset in
PAE
AB
Register. The default offset value for
PAE
AB
Register is 8.
PAE
AB
is synchronized to CLK
B
.
When
PAF
AB
is LOW, the A
→
B FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into
PAF
AB
Register. When PAF
AB
is HIGH,
the A
→
B FIFO contains less than or equal to the depth minus the offset in PAF
AB
Register.
The default offset value for PAF
AB
Register is 8.
PAF
AB
is synchronized to CLK
A
.
When
FF
AB
is LOW, the A
→
B FIFO is full and further data writes into Port A are inhibited.
When
FF
AB
is HIGH, the FIFO is not full.
FF
AB
is synchronized to CLK
A
. In bypass mode,
FF
AB
tells Port A that a message is waiting in Port B’s output register. If
FF
AB
is LOW, a
bypass message is in the register. If
FF
AB
is HIGH, Port B has read the message and another
message can be written into Port A.
When
EF
BA
is LOW, the B
→
A FIFO is empty and further data reads from Port A are inhibited.
When
EF
BA
is HIGH, the FIFO is not empty.
EF
BA
is synchronized to CLK
A
. In the bypass
mode,
EF
BA
HIGH indicates that data D
B0
-D
B17
is available for passing through. After the
data D
A0
-D
A17
has been read,
EF
BA
goes LOW on the following cycle.
When
PAE
BA
is LOW, the B
→
A FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into
PAE
BA
Register. When
PAE
BA
is HIGH, the
B
→
A FIFO contains more than offset in
PAE
BA
Register. The default offset value for
PAE
BA
Register is 8.
PAE
BA
is synchronized to CLK
A
.
When
PAF
BA
is LOW, the B
→
A FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into
PAF
BA
Register. When
PAF
BA
is HIGH,
the B
→
A FIFO contains less than or equal to the depth minus the offset in
PAF
BA
Register.
The default offset value for
PAF
BA
Register is 8.
PAF
BA
is synchronized to CLK
B
.
CLK
A
Clock A
I
EN
A
Enable A
I
OE
A
Output Enable A
I
A
0
, A
1
, A
2
D
B0
-D
B17
R/
W
B
Addresses
Data B
Read/Write B
I
I/O
I
CLK
B
Clock B
I
EN
B
Enable B
I
OE
B
Output Enable B
I
EF
AB
A
→
B Empty Flag
O
PAE
AB
A
→
B
Programmable
Almost-Empty Flag
O
PAF
AB
A
→
B
Programmable
Almost-Full Flag
O
FF
AB
A
→
B Full Flag
O
EF
BA
B
→
A Empty Flag
O
PAE
BA
B
→
A
Programmable
Almost-Empty Flag
O
PAF
BA
B
→
A
Programmable
Almost-Full Flag
O
2704 tbl 01
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT72615L25PF8 | 功能描述:IC FIFO BY SYNC 512X18X2 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72615L35J | 功能描述:IC FIFO BY SYNC 512X18X2 68PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72615L35J8 | 功能描述:IC FIFO BY SYNC 512X18X2 68PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72615L35PF | 功能描述:IC FIFO BY SYNC 512X18X2 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72615L35PF8 | 功能描述:IC FIFO BY SYNC 512X18X2 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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