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參數(shù)資料
| 型號(hào)： | IDT72605L35PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SyncBiFIFOO 256 x 18 x 2 and 512 x 18 x 2 |
| 中文描述： | 256 X 18 BI-DIRECTIONAL FIFO, 21 ns, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 209K |
| 代理商： | IDT72605L35PF |
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
5.18
7
NOTES:
1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.
2. Control A Consists of R/
W
A
,
EN
A
,
OE
A
,
CS
A
, A
2
, A
1
, A
0
. Control B consists of R/
W
B
,
EN
B
,
OE
B
.
Figure 1. 36- to 36-bit Processor Interface Configuration.
RESET
Reset is accomplished whenever the Reset (
RS
) input is
taken to a LOW state with
CS
A
,
EN
A
and
EN
B
HIGH. During
reset, both internal read and write pointers are set to the first
location. A reset is required after power up before a write
operation can take place. The A
→
B and B
→
A FIFO Empty
Flags (
EF
AB
,
EF
BA
) and Programmable Almost Empty Flags
(
PA
EAB
,
PA
EBA
) will be set to LOW after t
RSF
. The A
→
B and
B
→
A FIFO Full Flags (
FF
AB
,
FF
BA
) and Programmable Almost
Full Flags (
PAF
AB
,
PAF
BA
) will be set to HIGH after t
RSF
. After
the reset, the offsets of the Almost-Empty Flags and Almost-
Full Flags for the A
→
B and B
→
A FIFO offset default to 8.
PORT A INTERFACE
The SyncBiFIFO is straightforward to use in micro-pro-
cessor-based systems because each port has a standard
microprocessor control set. Port A interfaces with micropro-
cessor through the three address pins (A
2
-A
0
) and a Chip Select
CS
A
pins. When
CS
A
is asserted, A
2
,A
1
,A
0
and R/
W
A
are used
to select one of six internal resources (Table 1).
With A
2
=0 and A
1
=0, A
0
determines whether data can be
read out of output register or be written into the FIFO (A
0
=0),
or the data can pass through the FIFO through the bypass
path (A
0
=1).
With A
2
=1, four programmable flags (two A
→
B FIFO pro-
grammable flags and two B
→
A FIFO programmable flags)
can be selected: the A
→
B FIFO Almost-Empty Flag Offset
(A
1
=0, A
0
=0), A
→
B FIFO Almost-Full Flag Offset (A
1
=0, A
0
=1),
B
→
A FIFO Almost-Empty Flag Offset (A
1
=1, A
0
=0), B
→
A FIFO
Almost-Full Flag Offset (A
1
=1, A
0
=1).
Port A is disabled when CSA is deasserted and data A is in
high-impedance state.
CLK
DATA
ADDR, I/0
CONTROL
LOGIC
RAM A
IDT
SYNCBIFIFO
DATA B
CLK
CONTROL B
B
SYSTEM
CLOCK A
CONTROL
LOGIC
CLK
MICROPROCESSOR
A
MICROPROCESSOR
B
DATA
ADDR, I/0
RAM B
SYSTEM
CLOCK B
IDT
SYNCBIFIFO
DATA B
CLK
CONTROL B
B
DATA A
CLK
CONTROL A
A
DATA A
CLK
CONTROL A
A
2704 drw 06
FUNCTIONAL DESCRIPTION
IDTs SyncBiFIFO is versatile for both multiprocessor and
peripheral applications. Data can be stored or retrieved from
two sources simultaneously.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Two Dual-Port FIFO
memory arrays are contained in the SyncBiFIFO; one data
buffer for each direction. Each port has its own independent
clock. Data transfers to the I/O registers are gated by the
enable signals. The transfer direction for each port is con-
trolled independently by a read/write signal. Individual output
enable signals control whether the SyncBiFIFO is driving the
data lines of a port or whether those data lines are in a high-
impedance state. The processor connected to Port A of the
BiFIFO can send or receive messages directly to the Port B
device using the 18-bit bypass path.
The SyncBiFIFO can be used in multiples of 18-bits. In a 36-
to 36-bit configuration, two SyncBiFIFOs operate in parallel.
Both devices are programmed simultaneously, 18 data bits to
each device. This configuration can be extended to wider bus
widths (54- to 54-bits, 72- to 72-bits, etc.) by adding more
SyncBiFIFOs to the configuration. Figure 1 shows multiple
SyncBiFIFOs configured for multiprocessor communication.
The microprocessor or microcontroller connected to Port A
controls all operations of the SyncBiFIFO. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B interfaces with a second processor. The Port B control
pins are inputs driven by the second processor.
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| IDT72605L35PF8 | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L50J | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L50J8 | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L50PF | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L50PF8 | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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