- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377420 > IDT72510L35J (INTEGRATED DEVICE TECHNOLOGY INC) Current-Mode PWM Controller 8-PDIP 0 to 70 PDF資料下載
參數(shù)資料
| 型號： | IDT72510L35J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Current-Mode PWM Controller 8-PDIP 0 to 70 |
| 中文描述： | 512 X 18 BI-DIRECTIONAL FIFO, 35 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 10/32頁 |
| 文件大小： | 440K |
| 代理商： | IDT72510L35J |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
5.31
10
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
PORT A RESOURCES
COMMAND OPERATIONS
CS
A
0
A
1
A
0
Read
Write
0
0
B
→
A FIFO
A
→
B FIFO
0
0
1
9-bit Bypass Path
9-bit Bypass Path
0
1
0
Configuration
Registers
Status Register
Disabled
Configuration
Registers
Command Register
Disabled
0
1
1
X
1
X
Command
Opcode
0000
0001
0010
0011
0100
0101
Function
Reset BiFIFO (see Table 3)
Select Configuration Register (see Table 4)
Load Reread Pointer with Read Pointer Value
Load Rewrite Pointer with Write Pointer Value
Load Read Pointer with Reread Pointer Value
Load Write Pointer with Rewrite Pointer Value
0110
0111
1000
Set DMA Transfer Direction (see Table 5)
Set Status Register Format (see Table 6)
Increment in byte for A
→
B FIFO Read Pointer
(Port B)
1001
Increment in byte for B
→
A FIFO Write Pointer
(Port B)
Clear Write Parity Error Flag
Clear Read Parity Error Flag
1010
1011
2669 tbl 03
Table 1. Accessing Port A Resources Using
CS
A
, A
0
, and A
1
2669 tbl 04
Table 2. Functions Performed by Port A Commands
Port B Write Pointer with the Rewrite Pointer. No command
operands are required to perform a reread/rewrite operation.
When Port B of the BiFIFO is in peripheral mode, the DMA
direction is controlled by the Command Register. Table 5
shows the Port B read/write DMA direction operands.
The BiFIFO supports two Status Register formats. Status
Register format 1 gives all the internal flag status, while Status
Register format 0 provides the data in the Odd Byte Register.
Table 6 gives the operands for selecting the appropriate
Status Register format. See Table 8 for the details of the two
Status Register formats.
Two commands are provided to increment the Port B Read
and Write Pointers in case reread/rewrite is performed.
Incrementing the pointers guarantees that pointers will be on
a word boundary when an odd number of bytes is transmitted
through Port B. No operands are required for these commands.
When parity check errors occur on Port B, a clear parity
error command is needed to remove the parity error. There are
no operands for these commands.
Bypass Path
The bypass path acts as a bidirectional bus transceiver
directly between Port A and Port B. The direct connection
requires that the Port A interface pins are inputs and the Port
B interface pins are outputs. The bypass path is 9 bits wide in
an 18- to 9-bit configuration or in a 36- to 9-bit configuration.
Only in the 36- to 18-bit configuration is the bypass path 18 bits
wide.
During bypass operations, the BiFIFOs must be pro-
grammed into peripheral interface mode. Bit 10 of Configura-
tion Register 5 (see Table 11) is set to
1
for peripheral interface
mode. In a 36- to 9-bit configuration, both Port B data buses
will be active. Data written into Port A will appear on both
master and slave Port B buses concurrently. To avoid Port B
bus contention, the data on D
A0
-D
A7
and D
A16
of both BiFIFOs
should be exactly the same. Data read from Port A will appear
on pins D
A0
-D
A7
and D
A16
of both BiFIFOs within the same 36-
bit word.
Command Register
Ten registers are accessible through Port A, a Command
Register, a Status Register, and eight Configuration Registers.
The Command Register is written by setting
CS
A
= 0, A
1
=
1, A
0
= 1. Commands written into the BiFIFO have a 4-bit
opcode (bit 8 – bit 11) and a 3-bit operand (bit 0 – bit 2) as
shown in Figure 5. The commands can be used to reset the
BiFIFO, to select the Configuration Register, to perform intel-
ligent reread/rewrite, to set the Port B DMA direction, to set the
Status Register format, to modify the Port B Read and Write
Pointers, and to clear Port B parity errors. The command
opcodes are shown in Table 2.
The reset command initializes different portions of the
BiFIFO depending on the command operand. Table 3 shows
the reset command operands.
The Configuration Register address is set directly by the
command operands shown in Table 4.
Intelligent reread/rewrite is performed by changing the Port
B Read Pointer with the Reread Pointer or by changing the
Reset
The IDT72510 and IDT72520 have a hardware reset pin
(
RS
) that resets all BiFIFO functions. A hardware reset re-
quires the following four conditions:
R
B
and
W
B
must be HIGH,
RER
and
REW
must be HIGH, LDRER and LDREW must be
LOW, and
DS
A
must be HIGH (Figure 9). After a hardware
reset, the BiFIFO is in the following state: Configuration
Registers 0-3 are
0000
H
, Configuration Register 4 is set to
COMMAND FORMAT
15
12
X
11
8
7
X
3
X
2
Command Operand
0
2669 tbl 05
Figure 5. Format for Commands Written into Port A
X
X
X
Command Opcode
X
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72510L50J | High-Performance Current-Mode PWM Controller 14-SOIC 0 to 70 |
| IDT72520 | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
| IDT72520L25J | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
| IDT72520L35J | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
| IDT72520L50J | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72605L20J | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20J8 | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L20PF | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20PF8 | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L25J | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。