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參數(shù)資料
| 型號： | IDT72510 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT |
| 中文描述： | 總線匹配雙向FIFO的512 × 18位。 1024 × 9位1024 × 18位。 2048 × 9位 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大?。?/td> | 440K |
| 代理商： | IDT72510 |
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5.31
12
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
Status Register
The Status Register reports the state of the programmable
flags, the DMA read/write direction, the Odd Byte Register
valid bit, and parity errors. The Status Register is read by
setting
CS
A
= 0, A
1
= 1, A
0
= 1 (see Table 1).
There are two Status Register formats that are set by a
Status Register format command. Format
0
stores the Odd
Byte Register data in the lower eight bits of the Status
Register, while format
1
reports the flag states and the DMA
read/write direction in the lower eight bits. The upper eight bits
are identical for both formats. The flag states, the parity errors,
the Odd Byte Register valid bit, and the Status Register format
are all in the upper eight bits of the Status Register. See Table
8 for both Status Register formats.
Configuration Registers
The eight Configuration Register formats are shown in
Table 9. Configuration Registers 0-3 contain the program-
mable flag offsets for the Almost Empty and Almost Full flags.
These offsets are set to
0
when a hardware reset or a software
reset all is applied. Note that Table 9 shows that Configuration
Registers 0-3 are 10 bits wide to accommodate the 1024
locations in each FIFO memory of the IDT72520. Only 9 least
significant bits are used for the 512 locations of the IDT72510;
the most significant bit, bit 9, must be set to
0
.
Configuration Register 4 is used to assign the internal flags
to the external flag pins (FLG
A
-FLG
D
). Each external flag pin
is assigned an internal flag based on the four bit codes shown
in Table 10. The default condition for Configuration Register
4 is
6420
H
as shown in Table 7. The default flag assignments
are: FLG
D
is assigned B
→
A
Full
, FLG
C
is assigned B
→
A
Empty
,
FLG
B
is assigned A
→
B
Full
, FLG
A
is assigned A
→
B
Empty
.
Bit
0
Signal
1
2
3
4
Odd Byte Register
5
6
7
8
Valid Bit
9
Write Parity Error
10
Read Parity Error
11
Status Register Format = 0
12
A
→
B Full Flag
13
A
→
B Almost-Full Flag
14
B
→
A Empty Flag
15
B
→
A Almost-Empty Flag
Bit
0
1
2
3
4
Signal
Reserved
Reserved
Reserved
DMA Direction
A
→
B Empty Flag
5
A
→
B Almost-Empty Flag
6
B
→
A Full Flag
7
B
→
A Almost-Full Flag
8
9
10
11
12
Valid Bit
Write Parity Error
Read Parity Error
Status Register Format = 1
A
→
B Full Flag
13
A
→
B Almost-Full Flag
14
B
→
A Empty Flag
15
B
→
A Almost-Empty Flag
2669 tbl 11
Configuration Register 5 is a general control register. The
format of Configuration Register 5 is shown in Table 11. Bit 0
sets the Intel-style interface (
R
B
,
W
B
) or Motorola-style inter-
face (
DS
B
, R/
W
B
) for Port B. Bit 1 changes the byte order for
data coming through Port B. Bits 2 and 3 redefine Full and
Empty Flags for reread/rewrite data protection.
Bits 4-9 control the DMA interface and are only applicable
in peripheral interface mode. In processor interface mode,
these bits are don’t care states. Bits 4 and 5 set the polarity
of the DMA control pins REQ and ACK, respectively. An
internal clock controls all DMA operations. This internal clock
is derived from the external clock (CLK). Bit 9 determines the
internal clock frequency: the internal clock = CLK or the
internal clock = CLK divided by 2. Bit 8 sets whether
R
B
,
W
B
,
and
DS
B
are asserted for either one or two internal clocks. Bits
6 and 7 set the number of internal clocks between REQ
assertion and ACK assertion. The timing can be from 2 to 5
cycles as shown in Figure 17.
Bit 10 controls Port B processor or peripheral interface
mode. In processor mode, the Port B control pins (
R
B
,
W
B
,
DS
B
,
R/
W
B
) are inputs and the DMA controls are ignored. In
peripheral mode, the Port B control pins are outputs and the
DMA controls are active.
Bits 11 and 12 set the width expansion mode. For 18- to
9-bit configurations or 36- to 18-bit configurations, the BiFIFO
should be set in stand-alone mode. For a 36- to 9-bit
configuration, one BiFIFO must be in slave mode and the
other BiFIFO must be in master mode. The master BiFIFO
allows the first two bytes transferred across Port B to go to the
slave BiFIFO, then the next two bytes go to the master BiFIFO.
Configuration Register 7 controls the parity functions of
Port B as shown in Table 12. Either parity generation or parity
STATUS REGISTER FORMAT 0
STATUS REGISTER FORMAT 1
2669 tbl 12
Table 8. The Two Status Register Formats
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72511 | High-Performance Current-Mode PWM Controller 8-SOIC 0 to 70 |
| IDT72511L25G | High-Performance Current-Mode PWM Controller 14-SOIC 0 to 70 |
| IDT72511L25GB | High-Performance Current-Mode PWM Controller 8-SOIC 0 to 70 |
| IDT72511L25J | High-Performance Current-Mode PWM Controller 14-SOIC 0 to 70 |
| IDT72511L25JB | High-Performance Current-Mode PWM Controller 8-SOIC 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72510L35J | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72605L20J | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20J8 | 功能描述:IC FIFO BI SYNC 256X18 68-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72605L20PF | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72605L20PF8 | 功能描述:IC FIFO BI SYNC 256X18 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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