IDT723652/723662/723672 CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 an" />
參數(shù)資料
型號: IDT723672L15PF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 25/29頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 16384X36 120QFP
標(biāo)準包裝: 45
系列: 7200
功能: 同步
存儲容量: 576K(16K x 36)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 托盤
其它名稱: 723672L15PF
5
COMMERCIALTEMPERATURERANGE
IDT723652/723662/723672 CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Symbol
Name
I/O
Description
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
Select
A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a
LOW level selects FIFO2 output register data for output.
MBB
Port B Mailbox
I
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
Select
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and a
LOW level selects FIFO1 output register data for output.
MBF1
Mail1 Register
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Flag
Writes to the mail1 register are inhibited while
MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH
transition of CLKB when a port B read is selected and MBB is HIGH.
MBF1 is set HIGH when FIFO1
is reset.
MBF2
Mail2 Register
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes
Flag
to the mail2 register are inhibited while
MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH
transition of CLKA when a port A read is selected and MBA is HIGH.
MBF2 is also set HIGH when
FIFO2 is reset.
RST1
FIFO1 Reset
I
ToresetFIFO1,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while
RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0 and FS1 for AFA
and
AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM.
RST2
FIFO2 Reset
I
ToresetFIFO2,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while
RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0 and FS1 for AFB
and
AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM.
W/
RA
Port A Write/
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
Read Select
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/
RA is HIGH.
W/RB
Port B Write/
I
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH
Read Select
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when
W/RB is LOW.
PIN DESCRIPTIONS (CONTINUED)
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