IDT723652/723662/723672 CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 " />
參數(shù)資料
型號(hào)： IDT723672L15PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 4/29頁(yè)
文件大?。?/td> 0K
描述： IC FIFO SYNC 16384X36 120QFP
標(biāo)準(zhǔn)包裝： 750
系列： 7200
功能： 同步
存儲(chǔ)容量： 576K（16K x 36）
數(shù)據(jù)速率： 67MHz
訪問(wèn)時(shí)間： 15ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 120-LQFP
供應(yīng)商設(shè)備封裝： 120-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱(chēng)： 723672L15PF8
12
COMMERCIALTEMPERATURERANGE
IDT723652/723662/723672 CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
a write pointer and read pointer comparator that indicates when the FIFO
memory status is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of the Output Ready
flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word
inmemoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles
of the port Clock that reads data from the FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
output register.
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW
if a word in memory is the next data to be sent to the FlFO output register and
two cycles of the port Clock that reads data from the FIFO have not elapsed
since the time the word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing clock occurs,
forcing the Empty Flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
attimetSKEW1 orgreaterafterthewrite. Otherwise,thesubsequentclockcycle
Synchronized
Number of Words in FIFO(1,2)
to CLKB
to CLKA
IDT723652
(3)
IDT723662
(3)
IDT723672
(3)
EFB/ORB
AEB
AFA
FFA/IRA
000
L
H
1 to X1
H
L
H
(X1+1) to [2,048-(Y1+1)]
(X1+1) to [4,096-(Y1+1)]
(X1+1) to [8,192-(Y1+1)]
H
(2,048-Y1) to 2,047
(4,096-Y1) to 4,095
(8,192-Y1) to 8,191
H
L
H
2,048
4,096
8,192
H
L
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flopstages.
This is done to improve flag signal reliability by reducing the probability of
metastable events when CLKA and CLKB operate asynchronously to one
another.
EFA/ORA,AEA,FFA/IRA,andAFAaresynchronizedtoCLKA. EFB/
ORB,
AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and 5
show the relationship of each port flag to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (
EFA/ORA, EFB/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready (ORA,
ORB) function is selected. When the Output Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
In the IDT Standard mode, the Empty Flag (
EFA,EFB)functionisselected.
When the Empty Flag is HIGH, data is available in the FIFO’s RAM for reading
to the output register. When the Empty Flag is LOW, the previous data word
is present in the FIFO output register and attempted FIFO reads are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
that reads data from its array. For both the FWFT and IDT Standard modes,
the FIFO read pointer is incremented each time a new word is clocked to its
outputregister. ThestatemachinethatcontrolsanOutputReadyflagmonitors
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by
AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from
port A.
4. The ORB and IRA functions are active during FWFT mode; the
EFB and FFA functions are active in IDT Standard mode.
TABLE 4 — FIFO1 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
Number of Words in FIFO(1,2)
to CLKA
to CLKB
IDT723652
(3)
IDT723662
(3)
IDT723672
(3)
EFA/ORA
AEA
AFB
FFB/IRB
000
L
H
1 to X2
H
L
H
(X2+1) to [2,048-(Y2+1)]
(X2+1) to [4,096-(Y2+1)]
(X2+1) to [8,192-(Y2+1)]
H
(2,048-Y2) to 2,047
(4,096-Y2) to 4,095
(8,192-Y2) to 8,191
H
L
H
2,048
4,096
8,192
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by
AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from
port A.
4. The ORA and IRB functions are active during FWFT mode; the
EFA and FFB functions are active in IDT Standard mode.
TABLE 5 — FIFO2 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
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