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參數(shù)資料
| 型號： | IDT723666L12PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/39頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 8192X36 128QFP |
| 標準包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 288K（8K x 36） |
| 數(shù)據(jù)速率： | 83MHz |
| 訪問時間： | 12ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723666L12PF8 |
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15
COMMERCIALTEMPERATURERANGE
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Port A (A0-A35) lines, (provided that Port A is set-up for read operation). If
during a Loop sequence the FIFO2 becomes empty, then the last word from
FIFO2 will continue to be clocked into FIFO1 until FIFO1 becomes full or until
the Loop function is stopped. The Loop feature can be useful when performing
systemdebuggingandremoteloopbacks. SeeFigures34and35forLoopback
timingdiagrams.
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flopstages.
This is done to improve flag signal reliability by reducing the probability of
metastableeventswhenCLKAoperatesasynchronouslywithrespecttoeither
CLKB or CLKC.
EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to
CLKA.
EFB/ORB and AEB are synchronized to CLKB. FFC/IRC and AFC
are synchronized to CLKC. Tables 5 and 6 show the relationship of each port
flag to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (
EFA/ORA, EFB/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready (ORA,
ORB) function is selected. When the Output Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
In the IDT Standard mode, the Empty Flag (
EFA,EFB)functionisselected.
When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory for
reading to the output register. When the Empty Flag is LOW, the previous data
word is present in the FIFO output register and attempted FIFO reads are
ignored.
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclockthat
reads data from its array. For both the FWFT and IDT Standard modes, the
FIFO read pointer is incremented each time a new word is clocked to its output
register. ThestatemachinethatcontrolsanOutputReadyflagmonitorsawrite
pointer and read pointer comparator that indicates when the FIFO memory
status is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted to
the FIFO output register in a minimum of three cycles of the Output Ready flag
synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
of the port clock that reads data from the FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
outputregister.
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW
if a word in memory is the next data to be sent to the FlFO output register and
twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince
the time the word was written. The Empty Flag of the FIFO remains LOW until
the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing
the Empty Flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
at time tSKEW1 orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figure 16, 17, 18 and 19).
FULL/INPUT READY FLAGS (
FFA/IRA, FFC/IRC)
These are dual purpose flags. In FWFT mode, the Input Ready (IRA and
IRC) function is selected. In IDT Standard mode, the Full Flag (
FFAandFFC)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthatwrites
data to its array. For both FWFT and IDT Standard modes, each time a word
is written to a FIFO, its write pointer is incremented. The state machine that
controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock have elapsed since
the next memory write location has been read. The second LOW-to-HIGH
transition on the Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figure 20, 21, 22, and 23).
ALMOST-EMPTY FLAGS (
AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
data from its array. The state machine that controls an Almost-Empty flag
monitors a write pointer and read pointer comparator that indicates when the
FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2. The
almost-emptystateisdefinedbythecontentsofregisterX1for
AEBandregister
X2for
AEA. TheseregistersareloadedwithpresetvaluesduringaFIFOreset,
programmed from Port A, or programmed serially (see the Almost-Empty flag
andAlmost-Fullflagoffsetprogrammingsection).AnAlmost-EmptyflagisLOW
when its FIFO contains X or less words and is HIGH when its FIFO contains
(X+1)ormorewords. AdatawordpresentintheFIFOoutputregisterhasbeen
read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe
writethatfilledthememorytothe(X+1)level. AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO
writethatfillsmemorytothe(X+1)level. ALOW-to-HIGHtransitionofanAlmost-
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figure 24 and 25).
ALMOST-FULL FLAGS (
AFA, AFC)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2. Thealmost-fullstate
isdefinedbythecontentsofregisterY1for
AFAandregisterY2forAFC. These
registers are loaded with preset values during a FlFO reset, programmed from
Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag
offset programming section). An Almost-Full flag is LOW when the number of
words in its FIFO is greater than or equal to (2,048-Y), (4,096-Y), or (8,192-
Y) for the IDT723656, IDT723666, or IDT723676 respectively. An Almost-Full
flagisHIGHwhenthenumberofwordsinitsFIFOislessthanorequalto[2,048-
(Y+1)], [4,096-(Y+1)], or [8,192-(Y+1)] for the IDT723656, IDT723666, or
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| IDT723666L15PF | 功能描述:IC FIFO SYNC 8192X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723666L15PF8 | 功能描述:IC FIFO SYNC 8192X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723672L12PF | 功能描述:IC FIFO SYNC 16384X36 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723672L12PF8 | 功能描述:IC FIFO SYNC 16384X36 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723672L12PQF | 功能描述:IC FIFO SYNC 16384X36 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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