參數(shù)資料
型號(hào): IDT723642L20PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
中文描述: 1K X 36 BI-DIRECTIONAL FIFO, 12 ns, PQFP120
封裝: TQFP-120
文件頁(yè)數(shù): 2/26頁(yè)
文件大小: 294K
代理商: IDT723642L20PF
5.22
2
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
Full and almost Empty) to indicate when a selected number of
words is stored in memory. Communication between each
port may bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has
been stored. Two or more devices may be used in parallel to
create wider data paths.
The IDT723622/723632/723642 is a synchronous (clocked)
FIFO, meaning each port employs a synchronous interface.
All data transfers through a port are gated to the LOW-to-
HIGH transition of a port clock by enable signals. The clocks
for each port are independent of one another and can be
NOTES:
1. NC – no internal connection
2. Uses Yamaichi socket IC51-1324-828
NC
NC
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
GND
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
NC
NC
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
NC
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
8
PQ132-1
3022 drw 02
N
N
N
V
C
C
E
W
/
C
G
I
O
A
A
V
C
M
M
R
F
G
F
R
M
M
A
A
V
C
O
I
C
W
R
A
E
C
G
1
1
1
1
1
1
1
1
1
9
8
7
6
5
4
3
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N
N
B
1
B
1
B
9
B
7
B
8
V
C
B
6
G
B
5
B
4
B
3
B
2
B
1
B
0
G
A
0
A
1
A
2
V
C
A
3
A
4
A
5
G
A
6
A
7
A
8
A
9
A
1
A
1
G
N
7
7
7
7
7
8
8
8
7
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
7
7
7
7
PIN CONFIGURATION
PQF Package
TOP VIEW
asynchronous or coincident. The enables for each port are
arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The Input Ready (IRA, IRB) and Almost-Full (
AFA
,
AFB
)
flags of a FIFO are two-stage synchronized to the port clock
that writes data into its array. The Output Ready (ORA, ORB)
and Almost-Empty (
AEA
,
AEB
) flags of a FIFO are two-stage
synchronized to the port clock that reads data from its array.
Offset values for the Almost-Full and Almost-Empty flags of
both FIFOs can be programmed from Port A.
The IDT723622/723632/723642 is characterized for op-
eration from 0
°
C to 70
°
C.
相關(guān)PDF資料
PDF描述
IDT723642L20PQF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
IDT723642L30PF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
IDT723642L30PQF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
IDT723641 Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC -40 to 105
IDT723631L15PF CMOS SyncFIFOO 512 x 36, 1024 x 36, 2048 x 36
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