參數(shù)資料
型號(hào)： IDT723636L15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
中文描述： 512 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝： TQFP-128
文件頁數(shù)： 13/35頁
文件大?。?/td> 563K
代理商： IDT723636L15PF
13
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TABLE 5 FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
TABLE 6 FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKB
Synchronized
to CLKA
Number of Words in FIFO Memory
(1,2)
IDT723626
(3)
0
1 to X1
(X1+1) to [256-(Y1+1)]
(256-Y1) to 255
256
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register
(no read operation necessary), it is not included in the FIFO memory count.
3. X1 is the almost-empty offset for FIFO1 used by
AEB
. Y1 is the almost-full offset for FIFO1 used by
AFA
. Both X1 and Y1 are selected during a FIFO1 reset or port A programmng.
4. The ORB and IRA functions are active during FWFT mode; the
EFB
and
FFA
functions are active in IDT Standard mode.
IDT723636
(3)
0
1 to X1
(X1+1) to [512-(Y1+1)]
(512-Y1) to 511
512
IDT723646
(3)
0
1 to X1
(X1+1) to [1,024-(Y1+1)]
(1,024-Y1) to 1,023
1,024
EFB
/ORB
L
H
H
H
H
AEB
AFA
H
H
H
L
L
FFA
/IRA
H
H
H
H
L
L
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation
necessary), it is not included in the FIFO memory count.
3. X2 is the almost-empty offset for FIFO2 used by
AEA
. Y2 is the almost-full offset for FIFO2 used by
AFC
. Both X2 and Y2 are selected during a FIFO2 reset or port A programmng.
4. The ORA and IRC functions are active during FWFT mode; the
EFA
and
FFC
functions are active in IDT Standard mode.
Synchronized
to CLKA
Synchronized
to CLKC
Number of Words in FIFO Memory
(1,2)
IDT723626
(3)
0
1 to X2
(X2+1) to [256-(Y2+1)]
(256-Y2) to 255
256
IDT723636
(3)
0
1 to X2
(X2+1) to [512-(Y2+1)]
(512-Y2) to 511
512
IDT723646
(3)
0
1 to X2
(X2+1) to [1,024-(Y2+1)]
(1,024-Y2) to 1,023
1,024
EFA
/ORA
L
H
H
H
H
AEA
L
L
H
H
H
AFC
H
H
H
L
L
FFC
/IRC
H
H
H
H
L
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages. This is done to improve flag signal reliability by reducing the probability
of metastable events when CLKA operates asynchronously with respect to
either CLKB or CLKC.
EFA
/ORA,
AEA
,
FFA
/IRA, and
AFA
are synchronized to
CLKA.
EFB
/ORB and
AEB
are synchronized to CLKB.
FFC
/IRC and
AFC
are
synchronized to CLKC. Tables 5 and 6 show the relationship of each port flag
to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (
EFA
/ORA,
EFB
/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready (ORA,
ORB) function is selected. When the Output Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
In the IDT Standard mode, the Empty Flag (
EFA
,
EFB
) function is selected.
When the Empty Flag is HIGH, data is available in the FIFO’s RAMmemory
for reading to the output register. When the Empty Flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
that reads data fromits array. For both the FWFT and IDT Standard modes, the
FIFO read pointer is incremented each time a new word is clocked to its output
register. The state machine that controls an Output Ready flag monitors a write
pointer and read pointer comparator that indicates when the FIFO memory
status is empty, empty+1, or empty+2.
In FWFT mode, fromthe time a word is written to a FIFO, it can be shifted
to the FIFO output register in a mnimumof three cycles of the Output Ready flag
synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
of the port clock that reads data fromthe FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until the
third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously
forcing the Output Ready flag HIGH and shifting the word to the FIFO output
register.
In IDT Standard mode, fromthe time a word is written to a FIFO, the
Empty Flag will indicate the presence of data available for reading in a
mnimumof two cycles of the Empty Flag synchronizing clock. Therefore,
an Empty Flag is LOW if a word in memory is the next data to be sent to the FlFO
output register and two cycles of the port Clock that reads data fromthe FIFO
have not elapsed since the time the word was written. The Empty Flag of the
FIFO remains LOW until the second LOW-to-HIGH transition of the synchro-
nizing clock
occurs, forcing the Empty Flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
clock begins the first synchronization cycle of a write if the clock transition occurs
at time t
SKEW1
or greater after the write. Otherwise, the subsequent clock cycle
can be
the first synchronization cycle (see Figures 16, 17, 18 and 19).
相關(guān)PDF資料
PDF描述
IDT723646 CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723646L12PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723646L15PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723626L12PF Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70
IDT723626L15PF Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723636L15PF8 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723641L15PF 功能描述:IC FIFO SYNC 1024X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723641L15PF8 功能描述:IC FIFO SYNC 1024X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723641L15PFG 功能描述:IC FIFO SYNC 1024X36 132-PQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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