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參數(shù)資料
| 型號： | IDT723636L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/35頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 512X36X2 128QFP |
| 標準包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 36.8K（512 x 36 x 2） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723636L15PF8 |
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15
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
data appear on A18-A35. (In this case, A0-A17 are indeterminate.) For a 9-
bit bus size, 9 bits of mailbox data appear on A18-A26. (In this case, A0-A17
and A27-A35 are indeterminate.)
The data in a mail register remains intact after it is read and changes only
whennewdataiswrittentotheregister.TheEndianSelectfeaturehasnoeffect
on mailbox data.
NotethatMBCmustbeHIGHduringMasterReset(until
FFA/IRAandFFC/
IRC go HIGH. MBA and MBB are don't care inputs during Master Reset. For
mail registers and mail register flag timing diagrams, see Figure 28 and 29.
BUS SIZING
Port B may be configured in either an 18-bit word or a 9-bit byte format
for data read from FIFO1. Port C may be configured in either an 18-bit word
or a 9-bit byte format for data written to FIFO2. The bus size can be selected
independently for Ports B and C. The level applied to the Port B Size Select
(SIZEB) input determines the Port B bus size and the level applied to the
Port C Size Select (SIZEC) input determines the Port C bus size. These
levels should be static throughout FIFO operation. Both bus size selections
are implemented at the completion of Master Reset, by the time the Full/
Input Ready flag is set HIGH, as shown in Figures 2 and 3.
Two different methods for sequencing data transfer are available for
Ports B and C regardless of whether the bus size selection is byte- or word-
size. They are referred to as Big-Endian (most significant byte first) and
Little-Endian (least significant byte first). The level applied to the Big-
Endian Select (BE) input during the LOW-to-HIGH transition of
MRS1 and
MRS2selectstheendianmethodthatwillbeactiveduringFIFOoperation.This
selection applies to both ports B and C. The endian method is implemented at
thecompletionofMasterReset,bythetimetheFull/InputReadyflagissetHIGH,
as shown in Figures 2 and 3 (see Endian Selection section).
Only36-bitlongworddataiswrittentoorreadfromthetwoFIFOmemories
onthesedevices.Bus-matchingoperationsaredoneafterdataisreadfromthe
FIFO1 RAM (Port B) and before data is written to the FIFO2 RAM (Port C).
The Endian Select operations are not available when transferring data via
mailboxregisters.Furthermore,boththeword-andbyte-sizebusselectionslimit
thewidthofthedatabusthatcanbeusedformailregisteroperations.Inthiscase,
onlythosebytelanesbelongingtotheselectedword-orbyte-sizebuscancarry
mailboxdata.Theremainingdataoutputswillbeindeterminate.Theremaining
data inputs will be don’t care inputs. For example, when a word-size bus is
selected on Port B, then mailbox data can be transmitted only from A0-A17 to
B0-B17. When a byte-size bus is selected on Port B, then mailbox data can be
transmitted only from A0-A8 to B0-B8. Similarly, when a word-size bus is
selected on Port C, then mailbox data can be transmitted only from C0-C17 to
A18-A35. When a byte-size bus is selected on Port C, then mailbox data can
be transmitted only from C0-C8 to A18-A26. (See Figures 28 and 29).
BUS-MATCHING FIFO1 READS
Data is read from the FIFO1 RAM in 36-bit long word increments. Since
Port B can have a byte or word size, only the first one or two bytes appear
on the selected portion of the FIFO1 output register, with the rest of the long
word stored in auxiliary registers. In this case, subsequent FIFO1 reads
output the rest of the long word to the FIFO1 output register in the order
shown by Figure 2.
When reading data from FIFO1 in byte format, the unused B9-B17
outputs are indeterminate.
BUS-MATCHING FIFO2 WRITES
Data is written to the FIFO2 RAM in 36-bit long word increments. Data
written to FIFO2 with a byte or word bus size stores the initial bytes or words
in auxiliary registers. The CLKC rising edge that writes the fourth byte or the
second word of long word to FIFO2 also stores the entire long word in the
FIFO2 memory. The bytes are arranged in the manner shown in Figure 3.
When writing data to FIFO2 in byte format, the unused C9-C17 inputs
are don't care inputs.
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| IDT723641L15PF | 功能描述:IC FIFO SYNC 1024X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723641L15PF8 | 功能描述:IC FIFO SYNC 1024X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723641L15PFG | 功能描述:IC FIFO SYNC 1024X36 132-PQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723641L15PFG8 | 功能描述:IC FIFO SYNC 1024X36 120-TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723641L15PQF | 功能描述:IC FIFO SYNC 1024X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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