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參數(shù)資料
| 型號： | IDT723631L20PQF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Quad, High Slew Rate, Single-Supply, Op Amp 14-PDIP 0 to 70 |
| 中文描述： | 512 X 36 OTHER FIFO, 13 ns, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 269K |
| 代理商： | IDT723631L20PQF |
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
5
Symbol
MBF2
Name
I/O
O
Description
Mail2 Register Flag
MBF2
is set LOW by the LOW-to-HIGH transition of CLKB that writes data to
the mail2 register.
MBF2
is set HIGH by a LOW-to-HIGH transition of CLKA
when a port-A read is selected and MBA is HIGH.
MBF2
is set HIGH by a
reset.
OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is
LOW, the FIFO is empty and reads are disabled. Ready data is present in the
output register of the FIFO when OR is HIGH. OR is forced LOW during the
reset and goes HIGH on the third LOW-to-HIGH transition of CLKB after a
word is loaded to empty memory.
When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-to-
HIGH transition of CLKB to reset the read pointer to the beginning retransmit
location and output the first selected retransmit data.
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while
RST
is LOW. The LOW-to-HIGH
transition of
RST
latches the status of FS0 and FS1 for
AF
and
AE
offset
selection.
When RTM is HIGH and valid data is present in the FIFO output register (OR
is HIGH), a LOW-to-HIGH transition of CLKB selects the data for the begin-
ning of a retransmit and puts the FIFO in retransmit mode. The selected word
remains the initial retransmit point until a LOW-to-HIGH transition of CLKB
occurs while RTM is LOW, taking the FIFO out of retransmit mode.
A HIGH selects a write operation and a LOW selects a read operation on
port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/
R
A is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on
port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when
W
/RB is LOW.
OR
Output-Ready Flag
O
RFM
Read From Mark
I
RST
Reset
I
RTM
Retransmit Mode
I
W/
R
A
Port-A Write/Read
Select
I
W
/RB
Port-B Write/Read
Select
I
PIN DESCRIPTION (CONTINUED)
3023 tbl 02
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723631L20PQFI | 功能描述:IC FIFO SYNC 512X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723632L12PF | 功能描述:IC FIFO SYNC 512X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723632L12PF8 | 功能描述:IC FIFO SYNC 512X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723632L12PQF | 功能描述:IC FIFO SYNC 512X36X2 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723632L15PF | 功能描述:IC FIFO SYNC 512X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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