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參數(shù)資料
| 型號： | IDT723631 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70 |
| 中文描述： | 的CMOS SyncFIFOO 512 × 36，1024 × 36，2048 × 36 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 269K |
| 代理商： | IDT723631 |
10
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
impedance control of the data outputs. If a port enable is LOW
during a clock cycle, the port chip select and write/read select
may change states during the setup- and hold time window of
the cycle.
When the output-ready (OR) flag is LOW, the next data
word is sent to the FIFO output register automatically by the
CLKB LOW-to-HIGH transition that sets the output-ready flag
HIGH. When OR is HIGH, an available data word is clocked
to the FIFO output register only when a FIFO read is selected
by the port-B chip select (
CSB
), write/read select (
W
/RB),
enable (ENB), and mailbox select (MBB).
SYNCHRONIZED FIFO FLAGS
Each IDT723631/723641/723651 FIFO flag is synchro-
nized to its port clock through at least two flip-flop stages. This
is done to improve the flags’ reliability by reducing the prob-
ability of metastable events on their outputs when CLKA and
CLKB operate asynchronously to one another. OR and
AE
are
synchronized to CLKB. IR and
AF
are synchronized to CLKA.
Table 4 shows the relationship of each flag to the number of
words stored in memory.
OUTPUT-READY FLAG (OR)
The output-ready flag of a FIFO is synchronized to the port
clock that reads data from its array (CLKB). When the output-
ready flag is HIGH, new data is present in the FIFO output
CSB
H
L
L
L
L
L
L
L
W
/RB
X
L
L
L
H
H
H
H
ENB
X
L
H
H
L
H
L
H
MBB
X
X
L
H
L
L
H
H
CLKB
X
X
↑
↑
X
↑
X
↑
B0-A35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO Output Register
Active, FIFO Output Register
Active, Mail1 Register
Active, Mail1 Register
Port Functions
None
None
None
Mail2 Write
None
FIFO read
None
Mail1 Read (Set
MBF1
HIGH)
Table 3. Port-B Enable Function Table
CSA
H
L
L
L
L
L
L
L
W/
R
A
X
H
H
H
L
L
L
L
ENA
X
L
H
H
L
H
L
H
MBA
X
X
L
H
L
L
H
H
CLKA
X
X
↑
↑
X
↑
X
↑
A0-A35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, Mail2 Register
Active, Mail2 Register
Active, Mail2 Register
Active, Mail2 Register
Port Functions
None
None
FIFO Write
Mail1 Write
None
None
None
Mail2 Read (Set
MBF2
HIGH)
Table 2. Port-A Enable Function Table
3023 tbl 09
3023 tbl 10
register. When the output-ready flag is LOW, the previous
data word is present in the FIFO output register and attempted
FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word
is clocked to its output register. The state machine that
controls an output-ready flag monitors a write-pointer and
read-pointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. From the time a word
is written to a FIFO, it can be shifted to the FIFO output register
in a minimum of three cycles of CLKB. Therefore, an output-
ready flag is LOW if a word in memory is the next data to be
sent to the FIFO output register and three CLKB cycles have
not elapsed since the time the word was written. The output-
ready flag of the FIFO remains LOW until the third LOW-to-
HIGH transition of CLKB occurs, simultaneously forcing the
output-ready flag HIGH and shifting the word to the FIFO
output register.
A LOW-to-HIGH transition on CLKB begins the first syn-
chronization cycle of a write if the clock transition occurs at
time t
SKEW1
or greater after the write. Otherwise, the subse-
quent CLKB cycle may be the first synchronization cycle (see
Figure 6).
INPUT READY FLAG (IR)
The input ready flag of a FIFO is synchronized to the port
clock that writes data to its array (CLKA). When the input-
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| IDT723631L15PF | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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| IDT723631L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 512X36 120-TQFP |
| IDT723631L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 512X36 120-TQFP |
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