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參數(shù)資料
| 型號： | IDT723613L15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36 |
| 中文描述： | 64 X 36 OTHER FIFO, 10 ns, PQFP120 |
| 封裝： | TQFP-120 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大小： | 193K |
| 代理商： | IDT723613L15PF |
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: V
CC
= 5.0V ±10%, T
A
= 0
°
C to +70
°
C; Industrial; V
CC
= 5.0V
±
10%,T
A
= 40
°
C to +85
°
C)
Commercial
IDT723613L15
Min.
–
15
6
6
4
5
Coml & Ind’l
(1)
IDT723613L20
Min.
–
20
8
8
5
5
Symbol
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
Parameter
Max.
66.7
–
–
–
–
–
Max.
50
–
–
–
–
–
Unit
MHz
ns
ns
ns
ns
ns
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA and CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
Setup Time, A
0
-A
35
before CLKA
↑
and B
0
-B
35
before CLKB
↑
Setup Time,
CSA
, W/
R
A, ENA, and MBA before CLKA
↑
;
CSB
,W/
R
B, and ENB before
CLKB
↑
Setup Time, SIZ0, SIZ1,and BE before CLKB
↑
Setup Time, SW0 and SW1 before CLKB
↑
Setup Time, ODD/
EVEN
and PGB before CLKB
↑
(2)
Setup Time,
RST
LOW before CLKA
↑
or CLKB
↑
(3)
Setup Time, FS0 and FS1 before
RST
HIGH
Hold Time, A
0
-A
35
after CLKA
↑
and B
0
-B
35
after CLKB
↑
Hold Time,
CSA
W/
R
A, ENA and MBA after CLKA
↑
;
CSB
, W/
R
B, and ENB after CLKB
↑
Hold Time, SIZ0, SIZ1, and
BE
after CLKB
↑
Hold Time, SW0 and SW1 after CLKB
↑
Hold Time, ODD/
EVEN
and PGB after CLKB
↑
(2)
Hold Time,
RST
LOW after CLKA
↑
or CLKB
↑
(3)
Hold Time, FS0 and FS1 after
RST
HIGH
t
SKEW1
(4)
Skew Time, between CLKA
↑
and CLKB
↑
for
EF
and
FF
t
SKEW2
(4)
Skew Time, between CLKA
↑
and CLKB
↑
for
AE
and
AF
t
SZS
t
SWS
t
PGS
t
RSTS
t
FSS
t
DH
t
ENH
t
SZH
t
SWH
t
PGH
t
RSTH
t
FSH
4
5
4
5
5
1
1
2
0
0
5
4
8
14
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5
7
5
6
6
1
1
2
0
0
6
4
8
16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a clock edge that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timng constraint for proper device operation and is only included to illustrate the timng relationship between CLKA cycle and CLKB cycle.
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相關代理商/技術參數(shù) |
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|---|---|
| IDT723613L15PF8 | 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L15PQF | 功能描述:IC CLOCKED FIFO 64X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723613L20PF | 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L20PF8 | 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L20PFI | 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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