參數(shù)資料
型號(hào): IDT72361315PF
廠商: Integrated Device Technology, Inc.
英文描述: Single Low-Power Operational Amplifier 5-SOT-23 -40 to 85
中文描述: 先進(jìn)先出的CMOS時(shí)鐘與巴士匹配和字節(jié)交換64 × 36
文件頁(yè)數(shù): 14/26頁(yè)
文件大小: 193K
代理商: IDT72361315PF
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Figure 3. Logic Diagram for SIZ0, SIZ1, and BE Register
MUX
G1
1
1
D Q
SIZ0 Q
SIZ1 Q
BE
Q
SIZ0
SIZ1
BE
CLKB
3145 fig02
constraints to the port B Clock (CLKB). These timng constraints only apply
for a rising clock edge used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port B
bus (B
0
-B
35
) to check parity and the circuit used to generate parity for the mail2
data is shared by the port A bus (A
0
-A
35
) to check parity. The shared parity
trees of a port are used to generate parity bits for the data in a mail register when
the port Chip Select (
CSA
,
CSB
) is LOW, Enable (ENA, ENB) is HIGH, and
Write/Read select (W/
R
A, W/
R
B) input is LOW, the mail register is selected (MBA
HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity
Generate select (PGA, PGB) is HIGH. Generating parity for mail register data
does not change the contents of the register.
相關(guān)PDF資料
PDF描述
IDT72361315PFI Single Low-Power Operational Amplifier 5-SOT-23 -40 to 85
IDT72361315PQF CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
IDT72361320PF High-Slew-Rate, Single-Supply Operational Amplifier 8-SOIC 0 to 70
IDT72361320PFI CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
IDT72361320PQF CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
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