參數(shù)資料
型號： IDT723612L15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： BiCMOS SyncBiFIFOO 64 x 36 x 2
中文描述： 64 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP120
封裝： TQFP-120
文件頁數(shù)： 5/29頁
文件大?。?/td> 350K
代理商： IDT723612L15PF
5
COMMERCIAL TEMPERATURE RANGE
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
PIN DESCRIPTION (CONTINUED)
SYMBOL
NAME
I/O
DESCRIPTION
MBB
Port-B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a port-B read or write
operation. When the B0-B35 outputs are active, a HIGH level on MBB selects
data from the mail1 register for output, and a LOW level selects FIFO1
output register data for output.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to
the mail1 register. Writes to the mail1 register are inhibited while
MBF1
is set
LOW.
MBF1
is set HIGH by a LOW-to-HIGH transition of CLKB when a port-
B read is selected and MBB is HIGH.
MBF1
is set HIGH when the device is
reset.
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to
the mail2 register. Writes to the mail2 register are inhibited while
MBF2
is set
LOW.
MBF2
is set HIGH by a LOW-to-HIGH transition of CLKA when a port-
A read is selected and MBA is HIGH.
MBF2
is set HIGH when the device is
reset.
Odd parity is checked on each port when ODD/
EVEN
is HIGH, and even
parity is checked when ODD/
EVEN
is LOW. ODD/
EVEN
also selects the
type of parity generated for each port if parity generation is enabled for a read
operation.
When any byte applied to terminals A0-A35 fails parity,
PEFA
is LOW.
(Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the
most significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/
EVEN
input. The parity trees
used to check the A0-A35 inputs are shared by the mail2 register to generate
parity if parity generation is selected by PGA. Therefore, if a mail2 read with
parity generation is setup by having W/
R
A LOW, MBA HIGH, and PGA HIGH,
the
PEFA
flag is forcedHIGH regardless of the A0-A35 inputs.
O
When any byte applied to terminals B0-B35 fails parity,
PEFB
is LOW.
(Port B) Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most
significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/
EVEN
input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate
parity if parity generation is selected by PGB. Therefore, if a mail1 read with
parity generation is setup by having W/
R
B LOW, MBB HIGH, and PGB HIGH,
the
PEFB
flag is forced HIGH regardless of the state of the B0-B35 inputs.
I
Parity is generated for data reads from port A when PGA is HIGH. Genera-
tion The type of parity generated is selected by the state of the ODD/
EVEN
input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The
generated parity bits are output in the most significant bit of each byte.
I
Parity is generated for data reads from port B when PGB s HIGH. The type of
parity generated is selected by the state of the ODD/
EVEN
input. Bytes are
organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
I
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while
RST
is LOW. This sets the
AFA
,
AFB
,
MBF1
, and
MBF2
flags HIGH and the
EFA
,
EFB
,
AEA
,
AEB
,
FFA,
and
FFB
flags LOW. The LOW-to-HIGH transition of
RST
latches the status of the
FS1 and FS0 inouts to select almost-full and almost-empty flag offset.
I
A HIGH selects a write operation and a LOW selects a read operation on
port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/
R
A is HIGH.
I
A HIGH selects a write operation and a LOW selects a read operation on
port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/
R
B is HIGH.
MBF1
Mail1 Register Flag
O
MBF2
Mail2 Register Flag
O
ODD/
EVEN
Odd/Even Parity
Select
I
PEFA
Port-A Parity Error
Flag
O
PEFB
Port-B Parity Error
Flag
PGA
Port-A Parity
PGB
Port-B Parity
Generation
RST
Reset
W/
R
A
Port-A Write/Read
Select
W/
R
B
Port-B Write/Read
Select
相關(guān)PDF資料
PDF描述
IDT723612L15PQF BiCMOS SyncBiFIFOO 64 x 36 x 2
IDT723612L20PF BiCMOS SyncBiFIFOO 64 x 36 x 2
IDT723612L20PQF BiCMOS SyncBiFIFOO 64 x 36 x 2
IDT723612L30PF BiCMOS SyncBiFIFOO 64 x 36 x 2
IDT723612L30PQF BiCMOS SyncBiFIFOO 64 x 36 x 2
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723612L15PF8 功能描述:IC FIFO 64X36X2 15NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723612L15PQF 功能描述:IC FIFO 64X36X2 15NS 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723612L15PQFG 功能描述:IC FIFO 64X36X2 15NS 132PQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723612L20PF 功能描述:IC FIFO 64X36X2 20NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723612L20PF8 功能描述:IC FIFO 64X36X2 20NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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