參數(shù)資料
型號： IDT723612
廠商： Integrated Device Technology, Inc.
英文描述： Single Low-Power Operational Amplifier 5-SOT-23 -40 to 85
中文描述： BiCMOS工藝SyncBiFIFOO 64 × 36 × 2
文件頁數(shù)： 4/29頁
文件大小： 350K
代理商： IDT723612
4
COMMERCIAL TEMPERATURE RANGE
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
Symbol
A0-A35
AEA
Name
Port-A Data
Almost-Empty Flag
I/O
I/O
O
Description
36-bit bidirectional data port for side A.
Programmable almost-empty flag synchronized to CLKA. It is LOW when
the number of words in the FIFO2 is less than or equal to the value in the
offset register, X.
Programmable almost-full flag synchronized to CLKB. It is LOW when the
number of words in FIFO1 is less than or equal to the value in the
offset register, X.
Programmable almost-full flag synchronized to CLKA. It is LOW when the
number of empty locations in FIFO1 is less than or equal to the value in the
offset register, X.
Programmable almost-full flag synchronized to CLKB. It is LOW when the
number of empty locations in FIFO2 is less than or equal to the value in the
offset register, X.
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port-
A and can be aynchronous or coincident to CLKB.
EFA
,
FFA
,
AFA
, and
AEA
are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port-
B and can be asynchronous or coincident to CLKA.
EFB
,
FFB
,
AFB
, and
AEB
are synchronized to the LOW-to-HIGH transition of CLKB.
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A. The A0-A35 outputs are in the high-impedance state
when
CSA
is HIGH.
B
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B. The B0-B35 outputs are in the high-impedance state
when
CSB
is HIGH.
EFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
EFA
is
LOW, FIFO2 is empty, and reads from its memory are disabled. Data can
be read from FIFO2 to the output register when
EFA
is HIGH.
EFA
is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after data is loaded into empty FIFO2 memory.
EFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
EFB
is
LOW, the FIFO1 is empty, and reads from its memory are disabled. Data
can be read from FIFO1 to the output register when
EFB
is HIGH.
EFB
is
forced LOW when the device is reset and is set HIGH by the second LOW-
to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B.
FFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
FFA
is
LOW, FIFO1 is full, and writes to its memory are disabled.
FFA
is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after reset.
FFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
FFB
is
LOW, FIFO2 is full, and writes to its memory are disabled.
FFB
is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after reset.
The LOW-to-HIGH transition of
RST
latches the values of FS0 and FS1,
which selects one of four preset values for the almost-full flag and almost-
empty flag.
A HIGH level on MBA chooses a mailbox register for a port-A read or write
operation. When the A0-A35 outputs are active, a HIGH level on MBA
selects data from the mail2 register for output, and a LOW level selects
FIFO2 output register data for output.
(Port A)
AEB
Port-B Almost-Empty
Flag
O
(PortB)
AFA
Port-A Almost-Full
Flag
O
(Port A)
AFB
Port-B Almost-Empty
Flag
O
(Port B)
B0-B35
CLKA
Port-B Data.
Port-A Clock
I/O
I
CLKB
Port-B Clock
I
CSA
Port-A Chip Select
I
CSB
Port-B Chip Select
I
EFA
Port-A Empty Flag
O
(Port A)
EFB
Port-B Empty Flag
O
(Port B)
ENA
Port-A Enable
I
ENB
Port-B Enable
I
FFA
Port-A Full Flag
O
(Port A)
FFB
Port-B Full Flag
O
(Port B)
FS1, FS0 Flag-Offset Selects
I
MBA
Port-A Mailbox Select
I
PIN DESCRIPTION
相關(guān)PDF資料
PDF描述
IDT723613L15PQFI CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
IDT723613L20PFI CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
IDT723613L20PQFI CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
IDT723613L20PF CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
IDT723613L20PQF CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723612L15PF 功能描述:IC FIFO 64X36X2 15NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723612L15PF8 功能描述:IC FIFO 64X36X2 15NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723612L15PQF 功能描述:IC FIFO 64X36X2 15NS 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723612L15PQFG 功能描述:IC FIFO 64X36X2 15NS 132PQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723612L20PF 功能描述:IC FIFO 64X36X2 20NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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