參數(shù)資料
型號: IDT72281L15TFI8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/26頁
文件大?。?/td> 0K
描述: IC FIFO 32768X18 LP 15NS 64QFP
標準包裝: 1,250
系列: 7200
功能: 同步
存儲容量: 589K(32K x 18)
數(shù)據速率: 67MHz
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 72281L15TFI8
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
2
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
DESCRIPTION (CONTINUED)
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
WEN
SEN
DC(1)
VCC
GND(2)
D8
D7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DNC(3)
GND
DNC(3)
VCC
DNC(3)
GND
DNC(3)
Q8
Q7
Q6
GND
WCLK
PRS
MRS
LD
FWFT/SI
GND
FF
/IR
PAF
HF
V
CC
PAE
EF
/OR
RCLK
REN
RT
OE
Q5
Q4
V
CC
Q3
Q2
GND
Q1
Q0
GND
D0
D1
D2
D3
D4
D5
D6
4675 drw 02
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge
of RCLK when REN is asserted. An Output Enable (OE) input is provided for
three-statecontroloftheoutputs.
The frequencies of both the RCLK and the WCLK signals may vary from 0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
of the one clock input with respect to the other.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectlyto
thedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoesnot
havetobeassertedforaccessingthefirstword.However,subsequentwords
writtentotheFIFOdorequireaLOWonRENforaccess. ThestateoftheFWFT/
SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcan
provide, the FWFT timing mode permits depth expansion by chaining FIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
TheseFIFOshavefiveflagpins,EF/OR(EmptyFlagorOutputReady),FF/
IR(FullFlagorInputReady),HF(Half-fullFlag),PAE(ProgrammableAlmost-
Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFFfunctions
are selected in IDT Standard mode. The IR andORfunctionsareselectedin
NOTES:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2. This pin may either be tied to GND or left open.
3. DNC = Do Not Connect.
PIN CONFIGURATIONS
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