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參數(shù)資料
型號: IDT72281L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 20/26頁
文件大小: 0K
描述: IC FIFO 32768X18 LP 15NS 64QFP
標(biāo)準(zhǔn)包裝: 750
系列: 7200
功能: 同步
存儲容量: 589K(32K x 18)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72281L15PF8
3
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
DESCRIPTION (CONTINUED)
Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
MASTER RESET (
MRS)
READ CLOCK (RCLK)
READ ENABLE (
REN)
OUTPUT ENABLE (
OE)
EMPTY FLAG/OUTPUT READY (
EF/OR)
PROGRAMMABLE ALMOST-EMPTY (
PAE)
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN)
LOAD (
LD)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE ALMOST-FULL (
PAF)
IDT
72281
72291
PARTIAL RESET (
PRS)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (
RT)
4675 drw 03
HALF-FULL FLAG (
HF)
SERIAL ENABLE(
SEN)
FWFT mode. HF, PAE andPAFarealwaysavailableforuse,irrespectiveof
timingmode.
PAE and PAF can be programmed independently to switch at any point in
memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag
switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two
defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127
or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset
at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith
the LD pin during Master Reset.
For serialprogramming,SENtogetherwithLDoneachrisingedgeofWCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
to load the offset registers via Dn. REN together with LD on each rising edge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023
withserialprogramming. Theflagsareupdatedaccordingtothetimingmode
anddefaultoffsetsselected.
The Partial Reset (PRS) also sets the read and write pointers to the first
locationofthememory. However,thetimingmode,partialflagprogramming
method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect. PRS is useful for resetting a device in mid-operation, when
reprogrammingpartialflagswouldbeundesirable.
TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan
once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit
operation by setting the read pointer to the first location of the memory array.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
The IDT72281/72291 are fabricated using high speed submicron CMOS
technology.
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