參數(shù)資料
型號(hào)： IDT72281L10TF8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 21/26頁
文件大?。?/td> 0K
描述： IC FIFO 32768X18 LP 10NS 64QFP
標(biāo)準(zhǔn)包裝： 1,250
系列： 7200
功能： 同步
存儲(chǔ)容量： 589K（32K x 18）
數(shù)據(jù)速率： 100MHz
訪問時(shí)間： 10ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱： 72281L10TF8
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
4
PIN DESCRIPTION
Symbol
Name
I/O
Description
D0–D8
DataInputs
I
Data inputs for a 9-bit bus.
MRS
MasterReset
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program-
mableflagdefaultsettings,andserialorparallelprogrammingoftheoffsetsettings.
PRS
PartialReset
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and
programmableflagsettingsareallretained.
RT
Retransmit
I
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, program
ming method, existing timing mode or programmable flag settings. RT is useful to reread data from
the first physical location of the FIFO.
FWFT/SI
FirstWordFall
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
Through/Serial In
thispinfunctionsasaserialinputforloadingoffsetregisters
WCLK
WriteClock
I
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming, and when enabled by SEN, the rising edge of
WCLKwritesonebitofdataintotheprogrammableregisterforserialprogramming.
WEN
WriteEnable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
Read Clock
I
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from
theprogrammableregisters.
REN
Read Enable
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE
OutputEnable
I
OE controls the output impedance of Qn.
SEN
SerialEnable
I
SENenablesserialloadingofprogrammableflagoffsets.
LD
Load
I
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023 and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
andreadingfromtheoffsetregisters.
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.
FF/IR
Full Flag/
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO
Input Ready
memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is
space available for writing to the FIFO memory.
EF/OR
EmptyFlag/
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO
OutputReady
memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there
isvaliddataavailableattheoutputs.
PAF
Programmable
O
PAF goes LOW if the number of words in the FIFO memory is more than total word capacity of the
Almost-FullFlag
FIFO minus the full offset value m, which is stored in the Full Offset register. There are two possible
default values for m: 127 or 1,023.
PAE
Programmable
O
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in
Almost-EmptyFlag
the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values
for n can be programmed into the device.
HF
Half-FullFlag
O
HF indicates whether the FIFO memory is more or less than half-full.
Q0–Q8
DataOutputs
O
Data outputs for a 9-bus
VCC
Power
+5 Volt power supply pins.
GND
Ground
Groundpins.
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