參數(shù)資料
型號: IDT72275L10PF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 16/25頁
文件大?。?/td> 0K
描述: IC FIFO 32768X18 LP 10NS 64-TQFP
標(biāo)準(zhǔn)包裝: 90
系列: 7200
功能: 同步
存儲容量: 589K(32K x 18)
數(shù)據(jù)速率: 100MHz
訪問時間: 10ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 托盤
其它名稱: 72275L10PF
23
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72275/72285
CMOS SuperSync FIFO 32,768 x 18 and 65,536 x 18
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertion to vary by one cycle between FIFOs. In IDT Standard mode, such
Figure 19. Block Diagram of 32,768 x 36 and 65,536 x 36 Width Expansion
problems can be avoided by creating composite flags, that is, ANDing EF of
every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
composite flags can be created by ORing OR of every FIFO, and separately
ORing IR of every FIFO.
Figure19,BlockDiagramof32,768x36and65,536x36WidthExpansion
demonstratesawidthexpansionusingtwoIDT72275/72285devices. D0-D17
from each device form a 36-bit wide input bus and Q0-Q17 from each device
form a 36-bit wide output bus. Any word width can be attained by adding
additionalIDT72275/72285devices.
WRITE CLOCK (WCLK)
m + n
m
n
MASTER RESET (
MRS)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (
WEN)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE (
PAF)
PROGRAMMABLE (
PAE)
EMPTY FLAG/OUTPUT READY (
EF/OR) #2
OUTPUT ENABLE (
OE)
READ ENABLE (
REN)
m
LOAD (
LD)
IDT
72275
72285
EMPTY FLAG/OUTPUT READY (
EF/OR) #1
PARTIAL RESET (
PRS)
IDT
72275
72285
4674 drw 22
FULL FLAG/INPUT READY (
FF/IR) #2
HALF-FULL FLAG (
HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (
RT)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
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