參數(shù)資料
型號: IDT72241L25LB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 4K X 9 OTHER FIFO, 15 ns, CQCC32
封裝: CERAMIC, LCC-32
文件頁數(shù): 5/14頁
文件大小: 234K
代理商: IDT72241L25LB
13
MILITARY, INDUSTRIAL AND
COMMERCIAL TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
configuration,theWriteEnable2/Load(WEN2/LD)pinissetLOWatResetso
thatthepinoperatesasacontroltoloadandreadtheprogrammableflagoffsets.
DEPTH EXPANSION - The IDT72421/72201/72211/72221/72231/72241/
72251 can be adapted to applications when the requirements are for greater
than 64/256/512/1,024/2,048/4,096/8,192 words. The existence of two
enable pins on the read and write port allow depth expansion. The Write
Enable 2/Load pin is used as a second write enable in a depth expansion
configurationthustheProgrammableflagsaresettothedefaultvalues. Depth
expansion is possible by using one enable input for system control while the
otherenableinputiscontrolledbyexpansionlogictodirecttheflowofdata. A
typicalapplicationwouldhavetheexpansionlogicalternatedataaccessfrom
one device to the next in a sequential manner. These devices operate in the
DepthExpansionconfigurationwhenthefollowingconditionsaremet:
1. The WEN2/ LD pin is held HIGH during Reset so that this pin operates a
secondWriteEnable.
2. External logic is used to control the flow of data.
Please see the Application Note "DEPTH EXPANSION OF IDT'S SYN-
CHRONOUSFIFOsUSINGTHERINGCOUNTERAPPROACH"fordetails
ofthisconfiguration.
Figure 15. Block Diagram of 64 x 18, 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18
Synchronous FIFO Used in a Width Expansion Configuration
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION - A single IDT72421/72201/72211/
72221/72231/72241/72251maybeusedwhentheapplicationrequirements
are for 64/256/512/1,024/2,048/4,096/8,192 words or less. When these
FIFOsareinaSingleDeviceConfiguration,theReadEnable2(REN2)control
inputcanbegrounded(seeFigure14). Inthisconfiguration,theWriteEnable
2/Load(WEN2/LD)pinissetLOWatResetsothatthepinoperatesasacontrol
toloadandreadtheprogrammableflagoffsets.
WIDTH EXPANSION CONFIGURATION - Word width may be increased
simply by connecting the corresponding input controls signals of multiple
devices. A composite flag should be created for each of the endpoint status
flags (EF and FF). The partial status flags (AE andAF) can be detected from
any one device. Figure 15 demonstrates a 18-bit word width by using two
IDT72421/72201/72211/72221/72231/72241/72251s. Any word width can
be attained by adding additional IDT72421/72201/72211/72221/72231/
72241/72251s.
When these FIFOs are in a Width Expansion Configuration, the Read
Enable 2 (REN2) control input can be grounded (see Figure 15). In this
Figure 14. Block Diagram of Single 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 Synchronous FIFO
DATA OUT (Q0 - Q8)
DATA IN (D0 - D8)
RESET (
RS)
READ CLOCK (RCLK)
READ ENABLE 1 (
REN1)
OUTPUT ENABLE (
OE)
EMPTY FLAG (
EF)
PROGRAMMABLE ALMOST-EMPTY (
PAE)
READ ENABLE 2 (
REN2)
WRITE CLOCK (WCLK)
WRITE ENABLE 1 (
WEN1)
WRITE ENABLE 2/LOAD (WEN2/
LD)
FULL FLAG (
FF)
PROGRAMMABLE ALMOST-FULL (
PAF)
IDT
72421
72201
72211
72221
72231
72241
72251
2655 drw 16
DATA IN (D)
WRITE CLOCK (WCLK)
18
9
RESET (
RS)
READ CLOCK (RCLK)
DATA OUT (Q)
9
18
READ ENABLE 2 (
REN2)
READ ENABLE 2 (
REN2)
WRITE ENABLE1 (
WEN1)
FULL FLAG (
FF) #1
PROGRAMMABLE (
PAF)
PROGRAMMABLE (
PAE)
EMPTY FLAG (
EF) #2
OUTPUT ENABLE (
OE)
READ ENABLE (
REN)
9
WRITE ENABLE2/LOAD (WEN2/
LD)
IDT
72421
72201
72211
72221
72231
72241
72251
FULL FLAG (
FF) #2
EMPTY FLAG (
EF) #1
RESET (
RS)
IDT
72421
72201
72211
72221
72231
72241
72251
2655 drw 17
相關(guān)PDF資料
PDF描述
IDT72851L25TFG 8K X 9 BI-DIRECTIONAL FIFO, 15 ns, PQFP64
IDT72T3675L4-4BB 8K X 36 OTHER FIFO, 3.4 ns, PBGA208
IDT72V2105L15PFI 3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO 131,072 x 18 262,144 x 18
IDT72V36100L15PFI 3.3 VOLT HIGH-DENSITY SUPERSYNC II⑩ 36-BIT FIFO
IDT72V36100L6BB 3.3 VOLT HIGH-DENSITY SUPERSYNC II⑩ 36-BIT FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72241L25PF 功能描述:IC FIFO 2048X18 SYNC 25NS 32QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K(1K x 18) 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(10x10) 包裝:托盤 其它名稱:72225LB10TF
IDT72241L25PF8 功能描述:IC FIFO 2048X18 SYNC 25NS 32QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K(1K x 18) 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(10x10) 包裝:托盤 其它名稱:72225LB10TF
IDT72241L25PFI 功能描述:IC FIFO 2048X18 SYNC 25NS 32QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K(1K x 18) 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(10x10) 包裝:托盤 其它名稱:72225LB10TF
IDT72241L25PFI8 功能描述:IC FIFO 2048X18 SYNC 25NS 32QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K(1K x 18) 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(10x10) 包裝:托盤 其它名稱:72225LB10TF
IDT72245LB10J 功能描述:IC FIFO 1024X18 SYNC 10NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF