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參數(shù)資料
| 型號(hào)： | IDT7223611L15PF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS SyncFIFO 64 x 36 |
| 中文描述： | 的CMOS SyncFIFO 64 × 36 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 236K |
| 代理商： | IDT7223611L15PF |
Integrated Device Technology, Inc.
FEATURES:
Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
64 x 36 storage capacity
Synchronous data buffering from Port A to Port B
Mailbox bypass register in each direction
Programmable Almost-Full (
AF
) and Almost-Empty (
AE
)
flags
Microprocessor Interface Control Logic
Full Flag (
FF
) and Almost-Full (
AF
) flags synchronized by
CLKA
Empty Flag (
EF
) and Almost-Empty (
AE
) flags synchro-
nized by CLKB
Passive parity checking on each Port
Parity Generation can be selected for each Port
Supports clock frequencies up to 67MHz
COMMERCIAL TEMPERATURE RANGE
MAY 1997
1997 Integrated Device Technology, Inc.
DSC-3024/4
IDT723611
CMOS SyncFIFO
64 x 36
Fast access times of 10ns
Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)
Low-power advanced CMOS technology
Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military elecrical specifications
DESCRIPTION:
The IDT723611 is a monolithic, high-speed, low-power,
CMOS Synchronous (clocked) FIFO memory which supports
clock frequencies up to 67MHz and has read access times as
fast as 10ns. The 64 x 36 dual-port FIFO buffers data from Port
A to Port B. The FIFO has flags to indicate empty and full
conditions, and two programmable flags, Almost-Full (
AF
) and
Almost-Empty (
AE
), to indicate when a selected number of
words is stored in memory. Communication between each
port can take place through two 36-bit mailbox registers. Each
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/
R
A
ENA
MBA
Mail 2
Register
Mail 1
Register
I
R
O
R
Write
Pointer
Read
Pointer
Status Flag
Logic
Port-A
Control
Logic
Reset
Logic
RST
PEFA
MBF2
CLKB
CSB
W/
R
B
ENB
MBB
Port-B
Control
Logic
MBF1
PEFB
EF
AE
36
B
0
- B
35
FF
AF
FS
0
FS
1
3024 drw 01
Programmable
Flag Offset
Registers
A
0
- A
35
Parity
Gen/Check
P
G
FIFO
ODD/
EVEN
PGA
Parity
Gen/Check
PGB
36
64 x 36
SRAM
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
1
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
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| IDT72240L15TP | 功能描述:IC FIFO 4KX8 SYNC 15NS 28DIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72240L25TP | 功能描述:IC FIFO 4KX8 SYNC 25NS 28DIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72241L10J | 功能描述:IC FIFO 2048X18 SYNC 10NS 32PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72241L10J8 | 功能描述:IC FIFO 2048X18 SYNC 10NS 32PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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