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參數(shù)資料
| 型號： | IDT72235LB15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
| 中文描述： | 2K X 18 OTHER FIFO, 10 ns, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 181K |
| 代理商： | IDT72235LB15PF |
3
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
Symbol
Name
I/O
Description
D0–D17
Data Inputs
I
Data inputs for a 18-bit bus.
RS
Reset
I
When
RS is set LOW, internal read and write pointers are set to the first location of the
RAM array,
FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an
initial WRITE after power-up.
WCLK
Write Clock
I
When
WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,
if the FIFO is not full.
WEN
Write Enable
I
When
WEN is LOW and LD is HIGH, data is written into the FIFO on every LOW-to-HIGH
transition of WCLK. When
WEN is HIGH, the FIFO holds the previous data. Data will not be
written into the FIFO if the
FF is LOW.
RCLK
Read Clock
I
When
REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the
FIFO is not empty.
REN
Read Enable
I
When
REN is LOW and LD is HIGH, data is read from the FIFO on every LOW-to-HIGH
transition of RCLK. When
REN is HIGH, the output register holds the previous data. Data will
not be read from the FIFO if the
EF is LOW.
OE
Output Enable
I
When
OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will
be in a high-impedance state.
LD
Load
I
When
LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers
on the LOW-to-HIGH transition of the WCLK, when
WEN is LOW. When LD is LOW,
data on the outputs Q0–Q11 is read from the offset and depth registers on the LOW-to-
HIGH transition of the RCLK, when
REN is LOW.
FL
First Load
I
In the single device or width expansion configuration,
FL is grounded. In the depth expansion
configuration,
FL is grounded on the first device (first load device) and set to HIGH for all other
devices in the Daisy Chain.
WXI
Write Expansion
I
In the single device or width expansion configuration,
WXI is grounded. In the depth
expansion configuration,
WXI is connected to WXO (Write Expansion Out) of the previous device.
RXI
Read Expansion
I
In the single device or width expansion configuration,
RXI is grounded. In the depth expansion
configuration,
RXI is connected to RXO (Read Expansion Out) of the previous device.
FF
Full Flag
O
When
FF is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF is HIGH, the FIFO is not full. FF is synchronized to WCLK.
EF
Empty Flag
O
When
EF is LOW, the FIFO is empty and further data reads from the output are inhibited.
When
EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
PAE
Programmable
O
When
PAE is LOW, the FIFO is almost empty based on the offset programmed into the
Almost-Empty Flag
FIFO. The default offset at reset is 31 from empty for IDT72205LB, 63 from empty for
IDT72215LB, and 127 from empty for IDT72225LB/72235LB/72245LB.
PAF
Programmable
O
When
PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO.
Almost-Full Flag
The default offset at reset is 31 from full for IDT72205LB, 63 from full for IDT72215LB, and
127 from full for IDT72225LB/72235LB/72245LB.
WXO/HF
Write Expansion
O
In the single device or width expansion configuration, the device is more than half full
Out/Half-Full Flag
when
HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to
WXI of the next device when the last location in the FIFO is written.
RXO
Read Expansion
O
In the depth expansion configuration, a pulse is sent from
RXO to RXI of the next device
Out
when the last location in the FIFO is read.
Q0–Q17
Data Outputs
O
Data outputs for a 18-bit bus.
VCC
Power
+5V power supply pins.
GND
Ground
Eight ground pins for the PLCC and seven pins for the TQFP/STQFP.
PIN DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72235LB15PFB | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
| IDT72235LB15PFI | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
| IDT72235LB15TF | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
| IDT72235LB15TFB | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
| IDT72235LB15TFI | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72235LB15PF8 | 功能描述:IC FIFO 2048X18 SYNC 15NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72235LB15PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 2048X18 SYNC 15NS 64TQFP |
| IDT72235LB15PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 2048X18 SYNC 15NS 64TQFP |
| IDT72235LB15PFI | 功能描述:IC FIFO 2048X18 SYNC 15NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72235LB15PFI8 | 功能描述:IC FIFO 2048X18 SYNC 15NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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