參數(shù)資料
型號(hào)： IDT72231L10PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 7/14頁(yè)
文件大?。?/td> 0K
描述： IC FIFO SYNC 512X9 10NS 32QFP
標(biāo)準(zhǔn)包裝： 2,000
系列： 7200
功能： 同步
存儲(chǔ)容量： 18K（2K x 9）
訪問時(shí)間： 10ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 32-LQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 帶卷 (TR)
其它名稱： 72231L10PF8
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
2
PIN CONFIGURATION
TQFP (PR32-1, order code: PF)
TOP VIEW
PLCC (J32-1, order code: J)
TOP VIEW
RS
WEN1
WCLK
WEN2/
LD
5
6
7
8
16
VCC
D0
PAF
PAE
GND
REN1
RCLK
REN2
27 26 25
24
23
22
21
29 28
32 31 30
9 1011 12131415
2655 drw 02
EF
OE
FF
1
2
3
4
20
19
18
17
INDEX
D1
Q
0
Q
1
Q
2
Q
3
Q
4
Q8
Q7
Q6
Q5
D
2
D
3
D
4
D
5
D
6
D
7
D
8
RS
WEN1
WCLK
WEN2/
LD
VCC
5
6
7
8
9
10
11
12
13
PAF
PAE
GND
REN1
RCLK
REN2
OE
27
26
25
24
23
22
21
29
28
432
1
32 31 30
14 15 16 17 18 19 20
D
2
FF
EF
INDEX
2655 drw02a
D
3
D
4
D
5
D
6
D
7
D
8
Q
0
Q
1
Q
2
Q
3
Q
4
Q8
Q7
Q6
Q5
D1
D0
Symbol
Name
I/O
Description
D0-D8
DataInputs
I Data inputs for a 9-bit bus.
RS
Reset
I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,FF and PAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLK
WriteClock
I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
WEN1
WriteEnable1
I If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin. When WEN1 is LOW,
data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write
enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW.
WEN2/
WriteEnable2/
I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/LD is HIGH
LD
Load
at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset, this pin operates as a control
to load and read the programmable flag offsets. If the FIFO is configured to have two write enables, WEN1 must
be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is
LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the
programmableflagoffsets.
Q0-Q8
DataOutputs
O Data outputs for a 9-bit bus.
RCLK
Read Clock
I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.
REN1
Read Enable 1
I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
REN2
Read Enable 2
I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
OE
OutputEnable
I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
EF
EmptyFlag
O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the
FIFO is not empty. EF is synchronized to RCLK.
PAE
Programmable
O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
Almost-EmptyFlag
offset at reset is Empty+7. PAE is synchronized to RCLK.
PAF
Programmable
O WhenPAFisLOW,theFIFOisalmost-fullbasedontheoffsetprogrammedintotheFIFO.Thedefaultoffset
Almost-FullFlag
at reset is Full-7. PAF is synchronized to WCLK.
FF
Full Flag
O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
is not full. FF is synchronized to WCLK.
VCC
Power
One +5 volt power supply pin.
GND
Ground
One 0 volt ground pin.
PIN DESCRIPTIONS
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