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參數(shù)資料
| 型號： | IDT72215LB25JI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 512X18 SYNC 25NS 68-PLCC |
| 標準包裝： | 250 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 9.2K（512 x 18） |
| 數(shù)據(jù)速率： | 40MHz |
| 訪問時間： | 25ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應商設備封裝： | 68-PLCC（24x24） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72215LB25JI8 |
6
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH 2013
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
RESET (RS)
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOWstate.
During reset, both internal read and write pointers are set to the first location.
Aresetisrequiredafterpower-upbeforeawriteoperationcantakeplace.The
FullFlag(FF),Half-FullFlag(HF)andProgrammableAlmost-FullFlag(PAF)
will be reset to HIGH after tRSF. The Empty Flag (EF) and Programmable
Almost-EmptyFlag(PAE)willberesettoLOWaftertRSF. Duringreset,theoutput
registerisinitializedtoallzerosandtheoffsetregistersareinitializedtotheirdefault
values.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock
(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH
transitionofWCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
WhentheWENinput isLOWandLDinputisHIGH,datamaybeloadedinto
the FIFO RAM array on the rising edge of every WCLK cycle if the device is
notfull. DataisstoredintheRAMarraysequentiallyandindependentlyofany
ongoing read operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
Topreventdataoverflow,FFwillgoLOW,inhibitingfurtherwriteoperations.
Upon the completion of a valid read cycle, FF will go HIGH allowing a write to
occur. The FF flag is updated on the rising edge of WCLK. WEN is ignored
when the FIFO is full.
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock (RCLK), when Output Enable (OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (REN)
WhenReadEnableisLOWand LDinputisHIGH,dataisloadedfromthe
RAM array into the output register on the rising edge of every RCLK cycle if
the device is not empty.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand
nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain
the previous data value.
Every word accessed at Qn, including the first word written to an empty
FIFO,mustberequestedusingREN. Whenthelastwordhasbeenreadfrom
theFIFO,theEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations.
REN is ignored when the FIFO is empty. Once a write is performed, EF will
go HIGH allowing a read to occur. The EF flag is updated on the rising edge
of RCLK.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receivedatafromtheoutputregister.WhenOEisdisabled(HIGH),theQoutput
databusisinahigh-impedancestate.
LOAD (LD)
The IDT72205LB/72215LB/72225LB/72235LB/72245LB devices con-
tain two 12-bit offset registers with data on the inputs, or read on the outputs.
When the Load (LD) pin is set LOW and WEN is set LOW, data on the inputs
D0-D11 is written into the Empty Offset register on the first LOW-to-HIGH
transition of the Write Clock (WCLK). When the LD pin and (WEN) are held
LOWthendataiswrittenintotheFullOffsetregisteronthesecondLOW-to-HIGH
transitionof(WCLK).Thethirdtransitionofthewriteclock(WCLK)againwrites
totheEmptyOffsetregister.
However,writingalloffsetregistersdoesnothavetooccuratonetime.One
ortwooffsetregisterscanbewrittenandthenbybringingtheLDpinHIGH,the
FIFOisreturnedtonormalread/writeoperation.WhentheLDpinissetLOW,
and WEN is LOW, the next offset register in sequence is written.
EMPTY OFFSET REGISTER
17
11
0
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
FULL OFFSET REGISTER
17
11
0
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
2766 drw 05
Figure 2. Write Offset Register
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
Figure 3. Offset Register Location and Default Values
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
LD
WEN
WCLK
Selection
0
Writingtooffsetregisters:
EmptyOffset
FullOffset
0
1
NoOperation
1
0
Write Into FIFO
1
NoOperation
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| IDT72215LB25PF | 功能描述:IC FIFO 512X18 SYNC 25NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72215LB25PF8 | 功能描述:IC FIFO 512X18 SYNC 25NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72215LB25PFI | 功能描述:IC FIFO 512X18 SYNC 25NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72215LB25PFI8 | 功能描述:IC FIFO 512X18 SYNC 25NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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