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參數(shù)資料
| 型號： | IDT72131 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| 中文描述： | CMOS并行到串行FIFO的2048 × 9 4096 × 9 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大小： | 126K |
| 代理商： | IDT72131 |
5.34
4
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0
°
C to +70
°
C)
Commercial
IDT72131L35
IDT72141L35
Min.
—
—
IDT72131L50
IDT72141L50
Min.
—
—
Symbol
t
S
t
SOCP
PARALLEL INPUT TIMINGS
t
DS
Data Set-up Time
t
DH
Data Hold Time
t
WC
Write Cycle Time
t
WPW
Write Pulse Width
t
WR
Write Recovery Time
t
WEF
Write High to
EF
HIGH
t
WFF
Write Low to
FF
LOW
t
WF
Write Low to Transitioning
HF
,
AEF
t
WPF
Write Pulse Width After
FF
HIGH
SERIAL OUTPUT TIMINGS
t
SOHZ
SOCP Rising Edge to SO at High-Z
(1)
t
SOLZ
SOCP Rising Edge to SO at Low-Z
(1)
t
SOPD
SOCP Rising Edge to Valid Data on SO
t
SOX
SOX Set-up Time to SOCP Rising Edge
t
SOCW
Serial In Clock Width HIGH/LOW
t
SOCEF
SOCP Rising Edge (Bit 0 - Last Word) to
EF
LOW
t
SOCFF
SOCP Rising Edge to
FF
HIGH
t
SOCF
SOCP Rising Edge to
HF
,
AEF
, HIGH
t
REFSO
Recovery Time SOCP After
EF
HIGH
RESET TIMINGS
t
RSC
Reset Cycle Time
t
RS
Reset Pulse Width
t
RSS
Reset Set-up Time
t
RSR
Reset Recovery Time
t
RSF1
Reset to
EF
and
AEF
LOW
t
RSF2
Reset to
HF
and
FF
HIGH
t
RSQL
Reset to Q LOW
t
RSQH
Reset to Q HIGH
RETRANSMIT TIMINGS
t
RTC
Retransmit Cycle Time
t
RT
Retransmit Pulse Width
t
RTS
Retransmit Set-up Time
t
RTR
Retransmit Recovery Time
DEPTH EXPANSION MODE TIMINGS
t
XOL
Read/Write to
XO
LOW
t
XOH
Read/Write to
XO
HIGH
t
XI
XI
Pulse Width
t
XIR
XI
Recovery Time
t
XIS
XI
Set-up Time
Parameter
Max.
22.2
50
Max.
15
40
Unit
MHz
MHz
Parallel Shift Frequency
Serial-Out Shift Frequency
18
0
45
35
10
—
—
—
35
—
—
—
—
—
30
30
45
—
30
5
65
50
15
—
—
—
50
—
—
—
—
—
45
45
65
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
—
5
8
—
—
—
35
16
22
18
—
—
20
30
30
—
5
5
—
5
10
—
—
—
50
26
22
18
—
—
25
40
40
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
35
35
10
—
—
20
20
—
—
—
—
45
45
—
—
65
50
50
15
—
—
35
35
—
—
—
—
65
65
—
—
ns
ns
ns
ns
ns
ns
ns
ns
45
35
35
10
—
—
—
—
65
50
50
15
—
—
—
—
ns
ns
ns
ns
—
—
35
10
15
35
35
—
—
—
—
—
50
10
15
50
50
—
—
—
ns
ns
ns
ns
ns
NOTE:
2751 tbl 07
1. Guaranteed by design minimum times, not tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72131L35P | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72131L50P | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72141 | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72141L35P | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72141L50P | 3/8 Pin 100mA Adjustable Positive Voltage Regulator 8-SOIC 0 to 125 |
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