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參數(shù)資料
| 型號： | IDT7210L55F |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR |
| 中文描述： | 16-BIT, DSP-MULTIPLIER ACCUMULATOR/SUMMER, CQFP64 |
| 封裝： | FP-64 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 167K |
| 代理商： | IDT7210L55F |
11.2
9
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
SET-UP, HOLD AND RELEASE TIMES
ENABLE AND DISABLE TIMES
PULSE WIDTH
PROPAGATION DELAY
2577 drw 06
2577 drw 07
2577 drw 08
2577 drw 09
2577 drw 10
2577 lnk 09
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。