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參數資料
| 型號： | IDT7203S120LB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 |
| 中文描述： | 2K X 9 OTHER FIFO, 120 ns, CQCC32 |
| 封裝： | LCC-32 |
| 文件頁數： | 11/14頁 |
| 文件大小： | 147K |
| 代理商： | IDT7203S120LB |
5.04
11
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 12. Block Diagram of 2048 x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used in Single Device Mode
IDT
7203/
7204/
7205/
7206
XI
XI
9
18
9
WRITE (
W
)
FULL FLAG (
FF
)
RESET (
RS
)
9
9
18
HF
HF
DATA
(D)
IN
READ (
R
)
EMPTY FLAG (
EF
)
RETRANSMIT (
RT
)
DATA
(Q)
OUT
IDT
7203/
7204/
7205/
7206
2661 drw 15
NOTE:
1. Flag detection is accomplished by monitoring the
FF
,
EF
and
HF
signals on either (any) device used in the width expansion configuration.
Do not connect any output signals together.
Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memory Used in Width Expansion Mode
WRITE (
W
)
DATA IN (D)
FULL FLAG (
FF
)
RESET (
RS
)
9
READ (
R
)
9
DATA OUT (Q)
EMPTY FLAG (
EF
)
RETRANSMIT (
RT
)
EXPANSION IN (
XI
)
(
HF
)
IDT
7203/
7204/
7205/
7206
(HALF–FULL FLAG)
2661 drw 14
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| IDT7204S120LB | CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 |
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| IDT7205L120LB | CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 |
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