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    參數資料
    型號: IDT7203L12TPG
    廠商: INTEGRATED DEVICE TECHNOLOGY INC
    元件分類: DRAM
    英文描述: CMOS ASYNCHRONOUS FIFO
    中文描述: 2K X 9 OTHER FIFO, 12 ns, PDIP28
    封裝: GREEN, PLASTIC, DIP-28
    文件頁數: 9/14頁
    文件大小: 122K
    代理商: IDT7203L12TPG
    9
    COMMERCIAL, INDUSTRIAL AND MILITARY
    TEMPERATURE RANGES
    IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
    2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
    APRIL 3, 2006
    Figure 9. Half-Full Flag Timing
    Figure 10. Expansion Out
    Figure 11. Expansion In
    OPERATING MODES:
    Care must be taken to assure that the appropriate flag is monitored by
    each system(i.e.
    FF
    is monitored on the device where
    W
    is used;
    EF
    is monitored
    on the device where
    R
    is used). For additional information on the IDT7203/7204/
    7205/7206/7207, refer to Tech Note 8:
    Operating FIFOs on Full and Empty
    Boundary Conditions
    and Tech Note 6:
    Designing with FIFOs.
    Single Device Mode
    A single IDT7203/7204/7205/7206/7207/7208 may be used when the
    application requirements are for 2,048/4,096/8,192/16,384/32,768/65,536 words
    or less. These FIFOs are in a Single Device Configuration when the Expansion
    In (
    XI
    ) control input is grounded (see Figure 12).
    Depth Expansion
    These FIFOs can easily be adapted to applications when the require-
    ments are for greater than 2,048/4,096/8,192/16,384/32,768/65,536 words.
    Figure 14 demonstrates Depth Expansion using three IDT7203/7204/7205/
    7206/7207/7208s. Any depth can be attained by adding additional IDT7203/
    7204/7205/7206/7207/7208s. These devices operate in the Depth Expansion
    mode when the following conditions are met:
    1. The first device must be designated by grounding the First Load (
    FL
    ) control
    input.
    2. All other devices must have
    FL
    in the HIGH state.
    3. The Expansion Out (
    XO
    ) pin of each device must be tied to the Expansion
    In (
    XI
    ) pin of the next device. See Figure 14.
    4. External logic is needed to generate a composite Full Flag (
    FF
    ) and Empty
    Flag (
    EF
    ). This requires the ORing of all
    EF
    s and ORing of all
    FF
    s (i.e. all
    must be set to generate the correct composite
    FF
    or
    EF
    ). See Figure 14.
    5. The Retransmt (
    RT
    ) function and Half-Full Flag (
    HF
    ) are not available in
    the Depth Expansion Mode.
    For additional information on the IDT7203/7204/7205/7206/7207, refer to
    Tech Note 9:
    Cascading FIFOs or FIFO Modules.
    W
    R
    HF
    HALF-FULL OR LESS
    MORE THAN HALF-FULL
    HALF-FULL OR LESS
    t
    RHF
    t
    WHF
    2661 drw11
    W
    R
    XO
    WRITE TO
    LAST PHYSICAL
    LOCATION
    t
    XOL
    t
    XOH
    READ FROM
    LAST PHYSICAL
    LOCATION
    2661 drw12
    t
    XOH
    t
    XOL
    W
    R
    XI
    WRITE TO
    FIRST PHYSICAL
    LOCATION
    READ FROM
    FIRST PHYSICAL
    LOCATION
    t
    XI
    t
    XIR
    2661 drw13
    t
    XIS
    t
    XIS
    相關PDF資料
    PDF描述
    IDT7203L12TPGI CMOS ASYNCHRONOUS FIFO
    IDT7203L15DG CMOS ASYNCHRONOUS FIFO
    IDT7203L15DGI CMOS ASYNCHRONOUS FIFO
    IDT7203L15JG CMOS ASYNCHRONOUS FIFO
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    參數描述
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