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參數(shù)資料
| 型號(hào)： | IDT71V416YL10PHGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) |
| 中文描述： | 3.3V的CMOS靜態(tài)RAM 4梅格（256K x 16位） |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 95K |
| 代理商： | IDT71V416YL10PHGI |
6.42
IDT71V416VS, IDT71V416VL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2
(1)
ADDRESS
OE
CS
DATA
OUT
6478 drw 07
(3)
DATA
VALID
t
AA
t
RC
t
OE
t
OLZ
BHE
,
BLE
(3)
t
ACS
(3)
t
BLZ
t
CLZ
(2)
t
BE
(2)
t
OH
t
OHZ(3)
t
CHZ(3)
t
BHZ(3)
OUT
NOTES:
1. A write occurs during the overlap of a LOW
CS
, LOW
BHE
or
BLE
, and a LOW
WE
.
2.
OE
is continuously HIGH. If during a
WE
controlled write cycle
OE
is LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the mnimumwrite pulse is as
short as the specified t
WP
.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the
CS
LOW or
BHE
and
BLE
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV fromsteady state.
Timing Waveform of Write Cycle No. 1 (
WE
Controlled Timing)
(1,2,4)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of
CS
,
BHE
, or
BLE
transition LOW; otherwise t
AA
is the limting parameter.
3. Transition is measured ±200mV fromsteady state.
ADDRESS
CS
DATA
IN
6478 drw 08
(5)
(5)
(5)
DATA
IN
VALID
t
WC
t
AS
t
WHZ
(2)
t
CW
t
CHZ
t
OW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
PREVIOUS DATA VALID
DATA VALID
BHE
,
BLE
t
BW
t
WP
(5)
t
BHZ
(3)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71V416YL10PHGI8 | 功能描述:IC SRAM 4MBIT 10NS 44TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤 |
| IDT71V416YL10Y | 功能描述:IC SRAM 4MBIT 10NS 44SOJ RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:閃存 - NAND 存儲(chǔ)容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| IDT71V416YL10Y8 | 功能描述:IC SRAM 4MBIT 10NS 44SOJ RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:閃存 - NAND 存儲(chǔ)容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| IDT71V416YL12BE | 功能描述:IC SRAM 4MBIT 12NS 48BGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤 |
| IDT71V416YL12BE8 | 功能描述:IC SRAM 4MBIT 12NS 48BGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤 |
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