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參數(shù)資料
| 型號： | IDT71V3579YSA75BGGI |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect |
| 中文描述： | 128K的米鼠36，256 × 18 3.3同步SRAM的3.3V的I / O的流量，通過輸出脈沖計數(shù)器，單周期取消 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 521K |
| 代理商： | IDT71V3579YSA75BGGI |
FEBRUARY 2005
DSC-5280/08
1
2005 Integrated Device Technology, Inc.
Features
N
128K x 36, 256K x 18 memory configurations
N
Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
Commercial and Industrial:
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
N
LBO
input selects interleaved or linear burst mode
N
Self-timed write cycle with global write control (
enable (
BWE
), and byte writes (
N
3.3V core power supply
N
Power down controlled by ZZ input
N
3.3V I/O
N
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
N
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
GW
), byte write
BW
x)
Pin Description Summary
A
0
-A
17
NOTE:
1.
BW
3
and
BW
4
are not applicable for the IDT71V3579.
Description
The IDT71V3577/79 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAMto gen-
erate a self-timed write based upon a decision which can be left until the
end of the write cycle.
The burst mode feature offers the highest level of performance to the
systemdesigner, as the IDT71V3577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address fromthe processor, initiating the
access sequence. The first cycle of output data will flow-through fromthe
array after a clock-to-data access time delay fromthe rising clock edge of
the same cycle. If burst mode operation is selected (
ADV
=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the
LBO
input pin.
The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mmx 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS
0
,
CS
1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power I/O Power
Supply
N/A
V
SS
Ground
Supply
N/A
5280 tbl 01
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
IDT71V3577S
IDT71V3579S
IDT71V3577SA
IDT71V3579SA
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