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參數(shù)資料
| 型號： | IDT71V2548SA150PF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Ceramic Conformally Coated / Radial 'Standard & High Voltage Golden Max'; Capacitance [nom]: 5600pF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic, Conformally Coated; Temperature Coefficient: C0G (NP0); Lead Style: Radial Leaded; Lead Dimensions: 0.200" Lead Spacing; Body Dimensions: 0.300" x 0.390" x 0.200"; Container: Bag; Qty per Container: 250 |
| 中文描述： | 128K的× 36，256 × 18 3.3同步ZBT SRAM的2.5VI / O的脈沖計數(shù)器輸出流水線 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 1004K |
| 代理商： | IDT71V2548SA150PF |
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6.42
12
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Burst Read Operation
(1)
Burst Write Operation
(1)
Write Operation
(1)
NOTES:
1. H = High; L = Low; X = Dont Care; Z = High Impedance..
2.
CE
= L is defined as
CE
1
= L,
CE
2
= L and CE
2
= H.
CE
= H is defined as
CE
1
= H,
CE
2
= H or CE
2
= L.
NOTES:
1. H = High; L = Low; X = Dont Care; Z = High Impedance.
2.
CE
= L is defined as
CE
1
= L,
CE
2
= L and CE
2
= H.
CE
= H is defined as
CE
1
= H,
CE
2
= H or CE
2
= L.
NOTES:
1. H = High; L = Low; X = Dont Care; = Dont Know; Z = High Impedance.
2.
CE
= L is defined as
CE
1
= L,
CE
2
= L and CE
2
= H.
CE
= H is defined as
CE
1
= H,
CE
2
= H or CE
2
= L.
Cycle
Address
R/
W
ADV/
LD
CE
(2)
CEN
BW
x
OE
I/O
Comments
n
A
0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
H
X
L
X
X
X
Clock Setup Valid, Advance Counter
n+2
X
X
H
X
L
X
L
Q
0
Address A
0
Read Out, Inc. Count
n+3
X
X
H
X
L
X
L
Q
0+1
Address A
0+1
Read Out, Inc. Count
n+4
X
X
H
X
L
X
L
Q
0+2
Address A
0+2
Read Out, Inc. Count
n+5
A
1
H
L
L
L
X
L
Q
0+3
Address A
0+3
Read Out, Load A
1
n+6
X
X
H
X
L
X
L
Q
0
Address A
0
Read Out, Inc. Count
n+7
X
X
H
X
L
X
L
Q
1
Address A
1
Read Out, Inc. Count
n+8
A
2
H
L
L
L
X
L
Q
1+1
Address A
1+1
Read Out, Load A
2
5294 tbl 14
Cycle
Address
R/
W
ADV/
LD
CE
(2)
CEN
BW
x
OE
I/O
Comments
n
A
0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
X
Clock Setup Valid
n+2
X
X
X
X
L
X
X
D
0
Write to Address A
0
5294 tbl 15
Cycle
Address
R/
W
ADV/
LD
CE
(2)
CEN
BW
x
OE
I/O
Comments
n
A
0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
H
X
L
L
X
X
Clock Setup Valid, Inc. Count
n+2
X
X
H
X
L
L
X
D
0
Address A
0
Write, Inc. Count
n+3
X
X
H
X
L
L
X
D
0+1
Address A
0+1
Write, Inc. Count
n+4
X
X
H
X
L
L
X
D
0+2
Address A
0+2
Write, Inc. Count
n+5
A1
L
L
L
L
L
X
D
0+3
Address A
0+3
Write, Load A
1
n+6
X
X
H
X
L
L
X
D
0
Address A
0
Write, Inc. Count
n+7
X
X
H
X
L
L
X
D
1
Address A
1
Write, Inc. Count
n+8
A
2
L
L
L
L
L
X
D
1+1
Address A
1+1
Write, Load A
2
5294 tbl 16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71V2548SA150PFI | 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs |
| IDT71V2546S150BQI | 20V N-Channel PowerTrench MOSFET; Package: TO-251(IPAK); No of Pins: 3; Container: Rail |
| IDT71V2546S150PF | 25V N-Channel PowerTrench MOSFET; Package: TO-251(IPAK); No of Pins: 3; Container: Rail |
| IDT71V2546S150PFI | 25V N-Channel PowerTrench MOSFET; Package: TO-251(IPAK); No of Pins: 3; Container: Rail |
| IDT71V2546SA | 25V N-Channel PowerTrench MOSFET; Package: TO-251(IPAK); No of Pins: 3; Container: Rail |
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|---|---|
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