參數(shù)資料
型號： IDT71T75702
廠商： Integrated Device Technology, Inc.
元件分類： 通用總線功能
英文描述： 512K x 36, 1M x 18 2.5V Synchronous ZBT⑩ SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs
中文描述： 為512k × 36，100萬× 18⑩為2.5V同步ZBT SRAM的2.5VI / O的突發(fā)反流，通過輸出
文件頁數(shù)： 1/26頁
文件大?。?/td> 645K
代理商： IDT71T75702
APRIL 2004
DSC-5319/08
1
2004 Integrated Device Technology, Inc.
A
0
-A
19
Address Inputs
Input
Synchronous
CE
1
, CE
2
,
CE
2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance Burst Address/Load NewAddress
Input
Synchronous
LBO
Linear/Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
N/A
TDI
Test Data Input
Input
N/A
TCK
TestClock
Input
N/A
TDO
TestData Output
Output
N/A
TRST
JTAG Reset(Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input/Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power I/O Power
Supply
Static
V
SS
Ground
Supply
Static
Pin Description Summary
The IDT71T75702/902 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (
CEN
) pin allows operation of the IDT71T75702/902
to be suspended as long as necessary. All synchronous inputs are
ignored when
CEN
is high and the internal device registers will hold their
previous values.
There are three chip enable pins (
CE
1
, CE
2
,
CE
2
) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/
LD
is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71T75702/902 have an on-chip burst counter. In the burst
mode, the IDT71T75702/902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO
input pin. The
LBO
pin selects between linear and
interleaved burst sequence. The ADV/
LD
signal is used to load a new
external address (ADV/
LD
= LOW) or increment the internal burst counter
(ADV/
LD
= HIGH).
The IDT71T75702/902 SRAMs utilize IDT’s high-performance
CMOS process, and are packaged in a JEDEC Standard 14mmx 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
Features
N
512K x 36, 1Mx 18 memory configurations
N
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
N
ZBT
TM
Feature - No dead cycles between write and read cycles
N
Internally synchronized output buffer enable eliminates the
need to control
OE
N
Single R/
W
(READ/WRITE) control pin
N
4-word burst capability (Interleaved or linear)
N
Individual byte write (
BW
1
-
BW
4
) control (May tie active)
N
Three chip enables for simple depth expansion
N
2.5V power supply (±5%)
N
2.5V (±5%) I/O Supply (V
DDQ
)
N
Power down controlled by ZZ input
N
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
N
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Description
The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1Mx 18.
They are designed to elimnate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBT
TM
, or Zero Bus Turnaround.
Address and control signals are applied to the SRAMduring one clock
cycle, and on the next clock cycle the associated data cycle occurs, be
it read or write.
IDT71T75702
IDT71T75902
512K x 36, 1M x 18
2.5V Synchronous ZBT SRAMs
2.5V I/O, Burst Counter
Flow-Through Outputs
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT71T75702S75BG 功能描述:IC SRAM 18MBIT 75NS 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI
IDT71T75702S75BG8 功能描述:IC SRAM 18MBIT 75NS 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI
IDT71T75702S75BGI 功能描述:IC SRAM 18MBIT 75NS 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI
IDT71T75702S75BGI8 功能描述:IC SRAM 18MBIT 75NS 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI
IDT71T75702S75PF 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI
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