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參數(shù)資料
| 型號： | IDT7188S70DB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS STATIC RAM 64K 16K x 4-BIT |
| 中文描述： | 16K X 4 STANDARD SRAM, 70 ns, CDIP22 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-22 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 88K |
| 代理商： | IDT7188S70DB |
6.42
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
7
Timing Waveform of Write Cycle No. 2 (
CS
Controlled Timing)
(1,2,3,5)
Ordering Information
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured fromthe earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals should not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±200mV fromsteady state.
CS
DATA
IN
ADDRESS
WE
t
WR
2989 drw 09
t
AW
t
DW
t
WC
t
CW
t
DH
t
AS
DATA VALID
,
X
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
B
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
D
300 mil Ceramic DIP (D22-1)
25
35
45
55
70
85
S
L
Standard Power
Low Power
7188
Speed in nanoseconds
2989 drw 10
Device
Type
,
IDT
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