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參數(shù)資料
| 型號(hào)： | IDT7187L55DB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | High-Performance Current-Mode PWM Controller 8-SOIC -40 to 85 |
| 中文描述： | 64K X 1 STANDARD SRAM, 55 ns, CDIP22 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-22 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 70K |
| 代理商： | IDT7187L55DB |
6.2
7
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1,2,3,4)
t
WC
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured
±
200mV from steady state with a 5pF load (including scope and jig).
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured
±
200mV from steady state with a 5pF load (including scope and jig).
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CONTROLLED TIMING)
(1,2,4)
t
WC
CS
2986 drw 09
t
AW
t
WR
t
DW
DATA
IN
ADDRESS
WE
t
WP
t
DH
DATA
OUT
t
WZ
t
OW
t
AS
(5)
VALID DATA
(5)
WR
t
CS
2986 drw 10
t
AW
t
DW
DATA
IN
ADDRESS
WE
t
CW
t
DH
AS
t
VALID DATA
(3)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7187S25DB | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT7187S45DB | 制造商:Integrated Device Technology Inc 功能描述:Static RAM, 64Kx1, 22 Pin, Ceramic, DIP |
| IDT7187S45PI | 制造商:Integrated Device Technology Inc 功能描述:7187S45PI |
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