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參數(shù)資料
| 型號： | IDT7142SA100F |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 2K X 8 DUAL-PORT SRAM, 100 ns, CQFP48 |
| 封裝： | 0.750 X 0.750 INCH, 0.110 INCH HEIGHT, CERAMIC, FP-48 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 175K |
| 代理商： | IDT7142SA100F |
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.02
10
TABLE I — NON-CONTENTION
READ/WRITE CONTROL
(4)
Left or Right Port
(1)
R/
W
CE
X
H
OE
X
D
0–7
Z
Function
Port Disabled and in Power-
Down Mode, I
SB2
or I
SB4
CE
R
=
CE
L
=
V
IH
, Power-Down
Mode, I
SB1
or I
SB3
Data Written Into Memory
(2)
DATA
OUT
Data in Memory Output on Port
(3)
Z
High Impedance Outputs
X
H
X
Z
L
H
H
L
L
L
X
L
H
DATA
IN
NOTES:
1. A
0L
– A
10L
≠
A
0R
– A
10R
.
2. If
BUSY
= L, data is not written.
3. If
BUSY
= L, data may not be valid, see t
WDD
and t
DDD
timing.
4. 'H' = V
IH
, 'L' = V
IL
, 'X' = DON’T CARE, 'Z' = High-impedance.
2654 tbl 12
FUNCTIONAL DESCRIPTION
The IDT7132/IDT7142 provides two ports with separate
control, address and I/O pins that permit independent access
for reads or writes to any location in memory. The IDT7132/
IDT7142 has an automatic power down feature controlled by
CE
. The
CE
controls on-chip power down circuitry that
permits the respective port to go into a standby mode when
not selected (
CE
=
V
IL
). When a port is enabled, access to the
entire memory array is permitted.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The busy pin can then
be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/
S
pin. Once in slave mode the
BUSY
pin operates solely as a write inhibit input pin. Normal
operation can be programmed by tying the
BUSY
pins High.
If desired, unintended write operations can be prevented to
a port by tying the busy pin for that port low.
The busy outputs on the IDT7132/IDT7142 RAM in master
mode, are pull-up type outputs and do not require pull up
resistors to operate. If these RAMs are being expanded in
depth, then the busy indication for the resulting array re-
quires the use of an external AND gate.
TRUTH TABLES
TABLE II — ADDRESS BUSY ARBITRATION
Inputs
A
0L
-A
10L
CE
L
CE
R
A
0R
-A
10R
BUSY
L(1)
X
X
NO MATCH
H
X
MATCH
X
H
MATCH
L
L
MATCH
Outputs
BUSY
R(1)
Function
Normal
Normal
Normal
Write Inhibit
(3)
H
H
H
(2)
H
H
H
(2)
2654 tbl 13
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs for IDT7130 (master). Both are
inputs for IDT7140 (slave).
BUSY
X
outputs on the IDT7130 are open
drain, not push-pull outputs. On slaves the
BUSY
X
input internally inhibits
writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either
BUSY
L
or
BUSY
R
= Low will result.
BUSY
L
and
BUSY
R
outputs can
not be low simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
BUSY
R
outputs are driving Low regard-
less of actual logic level on the pin.
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| IDT7142SA100J | 功能描述:IC SRAM 16KBIT 100NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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| IDT7142SA100L48B | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 16KBIT 100NS 48LCC |
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