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參數(shù)資料
| 型號： | IDT7142LA100CB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS |
| 中文描述： | 2K X 8 DUAL-PORT SRAM, 100 ns, CDIP48 |
| 封裝： | 0.620 X 2.430 INCH, 0.150 INCH HEIGHT, SIDE BRAZED, DIP-48 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 255K |
| 代理商： | IDT7142LA100CB |
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of
BUSY
Arbitration Controlled by
CE
Timing
(1)
Timing Waveform of
BUSY
Arbitration Controlled
by Address Match Timing
(1)
Truth Tables
Table I. Non-Contention Read/Write Control
(4)
Left or Right Port
(1)
NOTES:
1.
2.
3.
4.
A
0L
- A
10L
≠
A
0R
- A
10R
If
BUSY
= L, data is not written.
If
BUSY
= L, data may not be valid, see t
WDD
and t
DDD
timing.
'H' = V
IH
, 'L' = V
IL
, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
t
APS
(2)
ADDR
"A"
and
"B"
ADDRESSES MATCH
t
BAC
t
BDC
CE
"B"
CE
"A"
BUSY
"A"
2692 drw 13
BUSY
"B"
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
t
APS
(2)
ADDR
"A"
ADDR
"B"
2692 drw 14
t
BAA
t
BDA
t
RC
or t
WC
NOTES:
1.
2.
All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
If t
APS
is not satisified, the
BUSY
will be asserted on one side or the other, but there is no guarantee on which side
BUSY
will be asserted (7132 only).
R/
W
CE
OE
D
0-7
Function
X
H
X
Z
Port Disabled and in Power-Down Mode, I
SB2
or I
SB4
X
H
X
Z
CE
R
=
CE
L
= V
IH,
Power-Down Mode, I
SB1
or I
SB3
L
L
X
DATA
IN
Data on Port Written into Memory
(2)
H
L
L
DATA
OUT
Data in Memory Output on Port
(3)
X
L
H
Z
High Impedance Outputs
2692 tbl 12
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