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參數(shù)資料
| 型號(hào)： | IDT7140SA35CG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM |
| 中文描述： | 1K X 8 DUAL-PORT SRAM, 35 ns, CDIP48 |
| 封裝： | 0.620 X 2.430 INCH, 0.150 INCH HEIGHT, GREEN, SIDE BRAZED, DIP-48 |
| 文件頁(yè)數(shù)： | 8/19頁(yè) |
| 文件大?。?/td> | 149K |
| 代理商： | IDT7140SA35CG |
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IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
16
Truth Table I — Non-Contention Read/Write Control(4)
Truth Tables
Truth Table II — Interrupt Flag(1,4)
Truth Table III — Address BUSY
Arbitration
NOTES:
1. Pins
BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for
IDT7140 (slave).
BUSYX outputs on the IDT7130 are open drain, not push-pull
outputs. On slaves the
BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either
BUSYL or BUSYR = LOW will
result.
BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when
BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
NOTES:
1. A0L – A10L A0R – A10R.
2. If
BUSY = L, data is not written.
3. If
BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
NOTES:
1. Assumes
BUSYL = BUSYR = VIH
2. If
BUSYL = VIL, then No Change.
3. If
BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Inputs(1)
Function
R/
W
CE
OE
D0-7
X
H
X
Z
Port Disabled and in Power-Down Mode, ISB2 or ISB4
XH
X
Z
CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3
LL
X
DATAIN
Data on Port Written into Memory(2)
HL
L
DATAOUT
Data in Memory Output on Port
(3)
H
L
H
Z
High Impedance Outputs
2689 tbl 13
Left Port
Right Port
Function
R/
WL
CEL
OEL
A9L-A0L
INTL
R/
WR
CER
OER
A9R-A0R
INTR
L
X3FF
XXXX
X
L(2)
Set Right
INTR Flag
XX
X
L
3FF
H(3)
Reset Right
INTR Flag
XX
X
L(3)
L
X
3FE
X
Set Left
INTL Flag
XL
L
3FE
H(2)
X
XXX
Reset Left
INTL Flag
2689 tbl 14
Inputs
Outputs
Function
CEL
CER
A0L-A9L
A0R-A9R
BUSYL(1)
BUSYR(1)
X
NO MATCH
H
Normal
H
X
MATCH
H
Normal
X
H
MATCH
H
Normal
L
MATCH
(2)
Write Inhibit
(3)
2689 tbl 15
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| IDT7140SA35J | 功能描述:IC SRAM 8KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7140SA35J8 | 功能描述:IC SRAM 8KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7140SA35JI | 功能描述:IC SRAM 8KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7140SA35JI8 | 功能描述:IC SRAM 8KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7140SA35L48B | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 8KBIT 35NS 48LCC |
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