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參數(shù)資料
| 型號(hào)： | IDT7140 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | High Speed 1K X 8 Dual-Port Static RAM(高速1K×8雙端口靜態(tài)RAM) |
| 中文描述： | 高速每1000 × 8雙端口靜態(tài)存儲(chǔ)器（高速每1000 × 8雙端口靜態(tài)RAM）的 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 214K |
| 代理商： | IDT7140 |
IDT7130SA/LA AND IDT7140SA/LA
HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
6.01
17
FUNCTIONAL DESCRIPTION
The IDT7130/IDT7140 provides two ports with separate
control, address and I/O pins that permit independent access
for reads or writes to any location in memory. The IDT7130/
IDT7140 has an automatic power down feature controlled by
CE
. The
CE
controls on-chip power down circuitry that permits
the respective port to go into a standby mode when not
selected (
CE
= V
IH
). When a port is enabled, access to the
entire memory array is permitted.
INTERRUPTS
If the user chooses the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
INT
L
) is asserted when the right port
writes to memory location 3FE (HEX), where a write is defined
as the
CE
R
= R/
W
R
= V
IL
per Truth Table II. The left port clears
the interrupt by access address location 3FE access when
CE
L
=
OE
L =
V
IL,
R/
W
is a "don't care". Likewise, the right port
interrupt flag (
INT
R
) is asserted when the left port writes to
memory location 3FF (HEX) and to clear the interrupt flag
(
INT
R
), the right port must access the memory location 3FF.
The message (8 bits) at 3FE or 3FF is user-defined, since it is
an addressable SRAM location. If the interrupt function is not
used, address locations 3FE and 3FF are not used as mail
boxes, but as part of the random access memory. Refer to
Truth Table II for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The
BUSY
pin
can then be used to stall the access until the operation on the
other side is completed. If a write operation has been at-
tempted from the side that receives a
BUSY
indication, the
write signal is gated internally to prevent the write from
proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the
BUSY
outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. In slave mode the
BUSY
pin operates solely as a
write inhibit input pin. Normal operation can be programmed
by tying the
BUSY
pins HIGH. If desired, unintended write
operations can be prevented to a port by tying the
BUSY
pin
for that port LOW.
The
BUSY
outputs on the IDT7130 RAM (Master) are open
2689 drw 18
MASTER
Dual Port
RAM
BUSY (L) BUSY (R)
CE
MASTER
Dual Port
RAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
CE
BUSY
L
BUSY
R
D
270
270
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7130 (Master) and IDT7140 (Slave)RAMs.
drain type outputs and require open drain resistors to operate.
If these RAMs are being expanded in depth, then the
BUSY
indication for the resulting array does not require the use of an
external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indica-
tion. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAMs the
BUSY
pin is an output if the part is Master (IDT7130), and the
BUSY
pin is an input if the part is a Slave (IDT7140) as shown in
Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The
BUSY
arbitration, on a Master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a
BUSY
flag to be
output from the master before the actual write pulse can be
initiated with either the R/
W
signal or the byte enables. Failure
to observe this timing can result in a glitched internal write
inhibit signal and corrupted data in the slave.
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| IDT7140LA100C | 功能描述:IC SRAM 8KBIT 100NS 48DIP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
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