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參數(shù)資料
| 型號： | IDT7134LA25PI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM |
| 中文描述： | 4K X 8 DUAL-PORT SRAM, 25 ns, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 160K |
| 代理商： | IDT7134LA25PI |
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
10
Truth Table I Read/Write Control
Left or Right Port
(1)
Functional Description
The IDT7134 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to any
location in memory. These devices have an automatic power down
feature controlled by
CE
. The
CE
controls on-chip power down circuitry
that permits the respective port to go into standby mode when not
selected (
CE
HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output Enable
control (
OE
). In the read mode, the ports
OE
turns on the output drivers
when set LOW. Non-contention READ/WRITE conditions are illustrated
in the table below.
Timing Waveform of Write Cycle No. 2,
CE
Controlled Timing
(1,4)
NOTES:
1. R/
W
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a
CE
=V
IL
and R/
W
= V
IL
.
3. t
WR
is measured from the earlier of
CE
or R/
W
going HIGH to the end-of-write cycle.
4. If the
CE
LOW transition occurs simultaneously with or after the R/
W
LOW transition, the outputs remain in the High-impedance state.
5. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
NOTE:
1. A
0L
- A
11L
≠
A
0R
- A
11R
"H" = V
IH
, "L" = V
IL
, "X" = Dont Care, and "Z" = High Impedance
R/
W
CE
OE
D
0-7
Function
X
H
X
Z
Port Deselected and in Power-Down
Mode, I
SB2
or I
SB4
X
H
X
Z
CE
R
=
CE
L
= H, Power Down
Mode I
SB1
or I
SB3
L
L
X
DATA
IN
Data on port written into memory
H
L
L
DATA
OUT
Data in memory output on port
X
X
H
Z
High impedance outputs
2720 tbl 11
2720 drw 12
R/
W
t
WC
ADDRESS
DATA
IN
CE
t
DW
t
WR
(3)
t
DH
t
EW
(2)
t
AW
t
AS
(5)
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| IDT7134LA35CI | HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7134LA35CB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 35NS SB48 |
| IDT7134LA35FB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 35NS 48FPACK |
| IDT7134LA35J | 功能描述:IC SRAM 32KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7134LA35J8 | 功能描述:IC SRAM 32KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7134LA35JI | 制造商:Integrated Device Technology Inc 功能描述: |
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