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參數(shù)資料
| 型號(hào)： | IDT7134LA25JI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM |
| 中文描述： | 4K X 8 DUAL-PORT SRAM, 25 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 160K |
| 代理商： | IDT7134LA25JI |
9
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
2720 drw 10
R/
W
"A"
(1)
VALID
t
WC
MATCH
VALID
MATCH
t
WP
t
DW
t
WDD
t
DDD
ADDR
"A"
DATA
IN "A"
DATA
OUT "B"
ADDR
"B"
t
AW
Timing Waveform of Write Cycle No. 1, R/
W
Controlled Timing
(1,5,8)
Timing Waveform of Write with Port-to-Port Read
(1,2,3)
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2.
CE
L =
CE
R =
V
IL.
OE
"B"
= V
IL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
NOTES:
1. R/
W
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a
CE
=V
IL
and R/
W
= V
IL
.
3. t
WR
is measured from the earlier of
CE
or R/
W
going to V
IH
to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the
CE
= V
IL
transition occurs simultaneously with or after the R/
W
= V
IL
transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load
(Figure 2).
8. If
OE
= V
IL
during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be placed on the bus
for the required t
DW
. If
OE
= V
IH
during an R
/W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
WP
.
CE
2720 drw 11
t
AW
t
AS
(6)
t
DW
DATA
IN
ADDRESS
t
WC
R/
W
t
WP
DATA
OUT
t
WZ
(7)
(4)
(4)
(2)
OE
t
HZ
(7)
t
LZ
(7)
t
HZ
t
WR
(3)
(7)
t
DH
t
OW
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