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參數(shù)資料
| 型號： | IDT71342SA55J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE |
| 中文描述： | 4K X 8 DUAL-PORT SRAM, 55 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 144K |
| 代理商： | IDT71342SA55J |
6.05
11
IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGE
TABLE I — NON-CONTENTION READ/WRITE CONTROL
Left or Right Port
(1)
CE
SEM
R/
W
X
H
X
u
OE
D
0-7
Z
Function
H
H
X
H
L
X
X
L
H
Port Disabled and in Power Down Mode
Data in Semaphore Flag Output on Port
Output Disabled
DATA
OUT
Z
H
L
X
DATA
IN
Port Data Bit D0 Written Into Semaphore Flag
H
L
X
L
L
L
H
H
L
L
X
X
DATA
OUT
DATA
IN
—
Data in Memory Output on Port
Data on Port Written Into Memory
Not Allowed
2721 tbl 13
NOTE:
1. A
OL
= A
10L
≠
A
0R
- A
10R.
"H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-impedance, and "
u
" = Low-to-High transition.
processor writes a zero in the left port at a free semaphore
location. On a subsequent read, the processor will verify that
it has written successfully to that location and will assume
control over the resource in question. Meanwhile, if a processor
on the right side attempts to write a zero to the same semaphore
flag it will fail, as will be verified by the fact that a one will be
read from that semaphore on the right side during a subsequent
read. Had a sequence of READ/WRITE been used instead,
system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 3. Two semaphore request latches feed into a
semaphore flag. Whichever latch is first to present a zero to
the semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will now stay low
until its semaphore request latch is written to a one. From this
it is easy to understand that, if a semaphore is requested and
the processor which requested it no longer needs the resource,
the entire can hang up until a one is written into that semaphore
request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
TABLE II — EXAMPLE SEMAPHORE PROCUREMENT SEQUENCE
(1,2)
Function
D
0
- D
7
Left
1
0
0
1
1
0
1
1
1
0
1
D
0
- D
7
Right
1
1
1
0
0
1
1
0
1
1
1
Status
No Action
Left Port Writes “0” to Semaphore
Right Port Writes “0” to Semaphore
Left Port Writes “1” to Semaphore
Left Port Writes “0” to Semaphore
Right Port Writes “1” to Semaphore
Left Port Writes “1” to Semaphore
Right Port Writes “0” to Semaphore
Right Port Writes “1” to Semaphore
Left Port Writes “0” to Semaphore
Left Port Writes “1” to Semaphore
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left side has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2721 tbl 14
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.
2. There are eight semaphore flags written to via I/O
0
and read from all I/O's (I/O
0
-I/O
7
). These eight semaphores are addressed by A
0
- A
2
.
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