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參數(shù)資料
| 型號(hào)： | IDT71342LA45J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 500V N-Channel MOSFET; Package: TO-220F; No of Pins: 3; Container: Rail |
| 中文描述： | 4K X 8 DUAL-PORT SRAM, 45 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大?。?/td> | 144K |
| 代理商： | IDT71342LA45J |
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IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGE
6.05
10
FUNCTIONAL DESCRIPTION
The IDT71342 is an extremely fast Dual-Port 4K x 8 CMOS
Static RAM with an additional 8 address locations dedicated
to binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAMs and can be read from or written to at the
same time, with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by
CE
, the Dual-Port RAM
enable, and
SEM
, the semaphore enable. The
CE
and
SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Table 1 where
CE
and
SEM
are both high.
Systems which can best use the IDT71342 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT71342’s hardware semaphores, which
provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT71342 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that a shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor had set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to gain
control of the token via the set and test sequence. Once the
right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT71342 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the
SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address,
OE
, and R/
W
) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through the address pins A
0
–A
2
. When accessing
the semaphores, none of the other address pins has any
effect.
When writing to a semaphore, only data pin D
0
is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other (see
Table II). That semaphore can now only be modified by the
side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this
feature follows shortly.) A zero written into the same location
from the other side will be stored in the semaphore request
latch for that side until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side’s output register when that side’s
semaphore select (
SEM
) and output enable (
OE
) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (
SEM
or
OE
)
to go inactive or the output will never change.
A sequence of WRITE/READ must be used by the
semaphore in order to guarantee that no system level
contention will occur. A processor requests access to shared
resources by attempting to write a zero into a semaphore
location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will
appear as a one, a fact which the processor will verify by the
subsequent read (see Table II). As an example, assume a
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PDF描述 |
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| IDT71342LA55J | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE |
| IDT71342LA55PF | 300V N-Channel MOSFET |
| IDT71342LA70J | 300V N-Channel MOSFET; Package: TO-220F; No of Pins: 3; Container: Rail |
| IDT71342LA70PF | 650V N-Channel MOSFET; Package: TO-220F; No of Pins: 3; Container: Rail |
| IDT71342SA | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE |
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