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參數(shù)資料
| 型號： | IDT7132LA55PI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS |
| 中文描述： | 高速2K × 8雙端口靜態(tài)RAM的中斷 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 255K |
| 代理商： | IDT7132LA55PI |
12
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and
BUSY
(2,3,4)
Timing Waveform of Write with
BUSY
(4)
NOTES:
1.
2.
3.
4.
t
WH
must be met for both
BUSY
Input (IDT7142, slave) or Output (IDT7132, master).
BUSY
is asserted on port "B" blocking R/
W
"B"
, until
BUSY
"B"
goes HIGH.
t
WB
applies only to the slave version (IDT7142).
All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
BUSY
"B"
2692 drw 12
R/
W
"A"
t
WP
t
WH
(1)
t
WB
R/
W
"B"
(2)
(3)
,
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
DATA
OUT"B"
DATA
IN"A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R/
W
"A"
BUSY
"B"
t
APS
(1)
2692 drw 11
t
BAA
NOTES:
1.
2.
3.
4.
To ensure that the earlier of the two ports wins.
t
APS
is ignored for Slave (IDT7142).
CE
L
=
CE
R
= V
IL
OE
= V
IL
for the reading port.
All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
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| IDT7132S90C | 制造商:Integrated Device Technology Inc 功能描述:Static RAM, 2Kx8, 48 Pin, Ceramic, DIP |
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| IDT7132SA100J8 | 功能描述:IC SRAM 16KBIT 100NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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