參數(shù)資料
型號(hào)： IDT7132LA100CB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
中文描述： 2K X 8 DUAL-PORT SRAM, 100 ns, CDIP48
封裝： 0.620 X 2.430 INCH, 0.150 INCH HEIGHT, SIDE BRAZED, DIP-48
文件頁(yè)數(shù)： 10/16頁(yè)
文件大?。?/td> 255K
代理商： IDT7132LA100CB
10
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/
W
Controlled Timing)
(1,5,8)
t
WC
ADDRESS
CE
R/
W
DATA
IN
t
AS
(6)
t
EW
(2)
t
WR
(3)
t
DW
t
DH
t
AW
2692 drw 10
Timing Waveform of Write Cycle No. 2, (
CE
Controlled Timing)
(1,5)
NOTES:
1. R/
W
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of
CE
= V
IL
and R/
W
= V
IL
.
3. t
WR
is measured from the earlier of
CE
or R/
W
going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the
CE
LOW transition occurs simultaneously with or after the R/
W
LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If
OE
is LOW during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be placed on the
bus for the required t
DW
. If
OE
is HIGH during a R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
WP
.
t
WC
ADDRESS
OE
CE
R/
W
DATA
OUT
DATA
IN
t
AS
(6)
t
OW
t
DW
t
DH
t
AW
t
WP
(2)
t
HZ
(7)
(4)
(4)
t
WZ
(7)
t
HZ
(7)
2692 drw 09
t
WR
(3)
相關(guān)PDF資料
PDF描述
IDT7142LA100CB HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT7132LA100CI HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT7142LA100CI HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT71421LA55TF HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT71421LA55TFI HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT7132LA100J 功能描述:IC SRAM 16KBIT 100NS 52PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR)
IDT7132LA100J8 功能描述:IC SRAM 16KBIT 100NS 52PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR)
IDT7132LA100L48B 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 16KBIT 100NS 48LCC
IDT7132LA100P 功能描述:IC SRAM 16KBIT 100NS 48DIP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR)
IDT7132LA20J 功能描述:IC SRAM 16KBIT 20NS 52PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):71V67703S75PFGI
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*