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參數(shù)資料
| 型號： | IDT7130SA35C |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 1K X 8 DUAL-PORT SRAM, 35 ns, CDIP48 |
| 封裝： | SIDE BRAZED, DIP-48 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 218K |
| 代理商： | IDT7130SA35C |
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.01
8
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
CE
CONTROLLED TIMING)
(1,5)
NOTES:
1. R/
W
or
CE
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of
CE
=
V
IL
and R/
W
=
V
IL.
3. t
WR
is measured from the earlier of
CE
or R/
W
going High to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the
CE
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If
OE
is low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off
and data to be placed on the bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and
the write pulse can be as short as the specified t
WP
.
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/
W
CONTROLLED TIMING)
(1,5,8)
t
WC
ADDRESS
OE
CE
R/
W
DATA
OUT
DATA
IN
t
AS
t
OW
t
DW
t
DH
t
AW
t
WP(2)
t
HZ
(4)
(4)
t
WZ
t
HZ
2689 drw 10
(6)
(7)
(7)
(3)
(7)
t
WR
t
WC
ADDRESS
CE
R/
W
DATA
IN
t
AS
t
EW
t
WR
t
DW
t
DH
t
AW
2689 drw 11
(6)
(2)
(3)
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| IDT7130SA35CB | HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM |
| IDT7130SA35F | HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM |
| IDT7130SA35FB | HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM |
| IDT7130SA35J | HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM |
| IDT7130SA35JB | HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7130SA35CB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 8KBIT 35NS SB48 |
| IDT7130SA35J | 功能描述:IC SRAM 8KBIT 35NS 52PLCC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-MSOP 包裝:帶卷 (TR) |
| IDT7130SA35J8 | 功能描述:IC SRAM 8KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應商設備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7130SA35L48B | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 8KBIT 35NS 48LCC |
| IDT7130SA35P | 功能描述:IC SRAM 8KBIT 35NS 48DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應商設備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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