參數(shù)資料
型號: IDT7130SA25PGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
中文描述: 1K X 8 DUAL-PORT SRAM, 25 ns, PDIP48
封裝: GREEN, PLASTIC, DIP-48
文件頁數(shù): 11/19頁
文件大?。?/td> 167K
代理商: IDT7130SA25PGI
11
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
T iming Waveform of Write Cycle No. 1, (R/
W
Controlled Timing)
(1,5,8)
T iming Waveform of Write Cycle No. 2, (
CE
Controlled Timing)
(1,5)
NOTES:
1. R/
W
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of
CE
=
V
IL
and R/
W
=
V
IL.
3. t
WR
is measured fromthe earlier of
CE
or R/
W
going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the
CE
LOW transition occurs simultaneously with or after the R/
W
LOW transition, the outputs remain in the HIGH impedance state.
6. Timng depends on which enable signal (
CE
or R/
W
) is asserted last.
7. This parameter is determned be device characterization, but is not production tested. Transition is measured 0mV fromsteady state with the Output Test Load
(Figure 2).
8. If
OE
is LOW during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be placed on the
bus for the required t
DW
. If
OE
is HIGH during a R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
WP
.
t
WC
ADDRESS
OE
CE
R/
W
DATA
OUT
DATA
IN
t
AS
(6)
t
OW
t
DW
t
DH
t
AW
t
WP
(2)
t
HZ
(7)
(4)
(4)
t
WZ
(7)
t
HZ
(7)
2689 drw 10
t
WR
(3)
t
WC
ADDRESS
CE
R/
W
DATA
IN
t
AS
(6)
t
EW
(2)
t
WR
(3)
t
DW
t
DH
t
AW
2689 drw 11
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