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參數(shù)資料
| 型號(hào)： | IDT71256L55Y |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS STATIC RAM 256K (32K x 8-BIT) |
| 中文描述： | 32K X 8 STANDARD SRAM, 55 ns, PDSO28 |
| 封裝： | 0.350 INCH, SOJ-28 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 78K |
| 代理商： | IDT71256L55Y |
7.2
7
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
TIMING WAVEFORM OF READ CYCLE NO. 3
(1, 3, 4)
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured
±
200mV from steady state.
2946 drw 07
ADDRESS
CS
DATA
OUT
t
RC
t
AA
t
OH
t
ACS
(5)
t
CLZ
t
CHZ(5)
t
OE
t
OLZ
(5)
t
OHZ(5)
OE
2946 drw 08
ADDRESS
t
RC
t
AA
t
OH
t
OH
DATA
OUT
2946 drw 09
DATA
OUT
CS
t
ACS
(5)
t
CLZ
(5)
t
CHZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71256L85D | Dual-Channel Pulse-Width-Modulation (PWM) Control Circuit 16-SSOP -20 to 85 |
| IDT71256L85DB | CMOS STATIC RAM 256K (32K x 8-BIT) |
| IDT71256L85L | CMOS STATIC RAM 256K (32K x 8-BIT) |
| IDT71256L85LB | Dual-Channel Pulse-Width-Modulation (PWM) Control Circuit 16-SOIC -20 to 85 |
| IDT71256L85P | CMOS STATIC RAM 256K (32K x 8-BIT) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71256L70DB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 70NS 28CDIP |
| IDT71256L70TDB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 70NS 28CDIP |
| IDT71256L85DB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 85NS 28CDIP |
| IDT71256L85TDB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 85NS 28CDIP |
| IDT71256S100DB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 100NS 28CDIP |
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